Nonvolatile memory apparatus

Abstract

A nonvolatile memory apparatus includes a sensing voltage generation unit, a memory cell, a current copy unit and a data sensing unit. The sensing voltage generation unit provides a sensing voltage with a constant level, to a sensing node. The memory cell receives the sensing voltage from the sensing node. The current copy unit generates copied current with substantially the same magnitude as sensing current which flows through the memory cell. The data sensing unit senses the copied current and generates a multi-bit data output signal.

1 . A nonvolatile memory apparatus comprising:
 a memory cell;   a sensing voltage generation unit configured to provide a sensing voltage with a constant level, to a sensing node;   a column switch configured to connect one end of the memory cell with a sensing node in response to a bit line select signal; and   a data sensing unit connected to the other end of the memory cell and configured to receive and sense sensing current which flows through the memory cell, from the other end of the memory cell in response to directly receiving a word line select signal, and generate a data output signal.   
     
     
         2 . The nonvolatile memory apparatus according to  claim 1 , wherein the sensing voltage generation unit comprises:
 a comparator configured to compare a reference voltage and a voltage of the sensing node and generate a comparison signal; and   a driver section configured to provide a power supply voltage to the sensing node in response to the comparison signal.   
     
     
         3 . The nonvolatile memory apparatus according to  claim 2 , wherein the driver section comprises a MOS transistor having a gate which receives the comparison signal, and a drain and a source one of which receives the power supply voltage and the other of which is connected with the sensing node. 
     
     
         4 . The nonvolatile memory apparatus according to  claim 1 , wherein the data sensing unit receives the sensing current when activated in response to the word line select signal, compares current flowing through the memory cell and reference cell current generated from a reference cell, and generate the data output signal. 
     
     
         5 . The nonvolatile memory apparatus according to  claim 1 , wherein the word line select signal is generated on the basis of a row address signal and is enabled for a shorter time than the bit line select signal. 
     
     
         6 . The nonvolatile memory apparatus according to  claim 4 , wherein the word line select signal is directly inputted to the data sensing unit.