System and method for modifying firmware used to initialize a computing device

Abstract

A system and method for patching a boot sequence in a read-only memory. Patch instances are provided in an addressable memory. The patch instances are initially empty. The read-only memory includes a process that dynamically vectors to identified locations in a set of addressable memory locations in the addressable memory. Thereafter, the process returns to the next subsequent instruction following the patch instance. As corrections are required, the one or more patch instances are populated with one or more respective patches. The boot sequence is modified by inserting one or more patch indicators located where patches might need to be applied after a system-on-chip (SoC) is embodied in firmware. The patches, when defined, are populated with at least an encoded instruction type and an address. Accordingly, a patch is enabled in no more than three words.

1 - 11 . (canceled) 
     
     
         12 . A system for patching a sequence of instructions stored in a read-only memory, the system comprising:
 a programmable read-only memory providing a set of addressable memory locations;   a read-only memory having stored therein a sequence of instructions and patch processing logic arranged to dynamically vector to identified locations in the set of addressable memory locations in the programmable read-only memory and return to the sequence of instructions in the read-only memory;   a random-access memory coupled to the programmable read-only memory and the read-only memory via a bus, the random-access memory arranged to store the sequence of instructions and the patch processing logic;   a controller for loading the sequence of instructions and the patch processing logic from the read-only memory to the random-access memory; and   a processor coupled to the random-access memory via the bus and configured to execute the sequence of instructions, wherein when a patch indicator is encountered in the sequence of instructions, the processor executes the patch processing logic.   
     
     
         13 . The system of  claim 12 , wherein the patch indicator is located at a place in the sequence of instructions where a required change is probable after the sequence of instructions is embodied in firmware. 
     
     
         14 . The system of  claim 12 , wherein a patch instance is stored in the programmable read-only memory, the patch instance including empty content before a modification to the sequence of instructions in the read-only memory is identified. 
     
     
         15 . The system of  claim 14 , wherein after a modification to the sequence of instructions in the read-only memory is identified, the patch instance includes at least a first word with an instruction type encoded therein and a second word with a patch address, the first word and the second word defining a patch. 
     
     
         16 . The system of  claim 15 , wherein the first word further includes mask information. 
     
     
         17 . The system of  claim 15 , wherein the patch is defined in words of N bits where N is an integer. 
     
     
         18 . The system of  claim 15 , wherein the patch includes replacement content only for the at least one patch indicator. 
     
     
         19 . The system of  claim 12 , wherein the patch processing logic directs the processor to access an address, determine if a patch is available at the address, when a patch is not available at the address, return to a next subsequent instruction in the sequence of instructions, otherwise, execute the instructions in the patch, and return to the next subsequent instruction in the sequence of instructions. 
     
     
         20 . The system of  claim 19 , further comprising:
 a set of one time programmable fuses coupled to the processor for providing patch data.   
     
     
         21 . A non-transitory processor-readable medium having stored thereon processor instructions that when executed direct the processor to perform functions, comprising:
 identifying when a patch indicator is present in a sequence of instructions;   determining when a patch instance is available at an address associated with the patch indicator, wherein when a patch instance is not available, loading a next subsequent instruction from the sequence of instructions;   otherwise, when a patch instance is available,   determining a patch type from information stored at the address associated with the patch indicator; and   executing one or more instructions in the patch instance.   
     
     
         22 . The non-transitory processor-readable medium of  claim 21 , wherein the determining when a patch instance is available is responsive to information communicated from a set of one-time programmable fuses. 
     
     
         23 . The non-transitory processor-readable medium of  claim 21 , wherein the patch indicator is located at a place in the sequence of instructions where a required change is probable after the sequence of instructions is embodied in firmware. 
     
     
         24 . The non-transitory processor-readable medium of  claim 21 , wherein a patch instance is stored in a programmable read-only memory, the patch instance including empty content before a modification to the sequence of instructions in the read-only memory is identified. 
     
     
         25 . The non-transitory processor-readable medium of  claim 21 , wherein after a modification to the sequence of instructions in the read-only memory is identified, the patch instance includes at least a first word with an instruction type encoded therein and a second word with a patch address, the first word and the second word defining a patch. 
     
     
         26 . The non-transitory processor-readable medium of  claim 25 , wherein the first word further includes mask information. 
     
     
         27 . The non-transitory processor-readable medium of  claim 25 , wherein the patch is defined in words of N bits where N is an integer. 
     
     
         28 . The non-transitory processor-readable medium of  claim 25 , wherein the patch includes replacement content only for the at least one patch indicator. 
     
     
         29 . A system for patching a sequence of instructions, the system comprising:
 a means for providing a set of addressable memory locations, having stored therein at least one patch instance;   a means for storing a sequence of instructions and patch processing logic arranged such that when executed by a processor direct the processor to dynamically vector to identified locations in the set of addressable memory locations and return to the sequence of instructions;   a means for temporarily storing the sequence of instructions and patch processing logic;   a means for loading the sequence of instructions and the patch processing logic from the means for storing to the means for temporarily storing; and   a means for executing the sequence of instructions from the means for temporarily storing, wherein when a patch indicator is encountered in the sequence of instructions, the means for executing executes the patch processing logic.   
     
     
         30 . The system of  claim 29 , wherein the means for executing the sequence of instructions identifies when a patch indicator is present in a sequence of instructions;
 determines when a patch instance is available at an address associated with the patch indicator, wherein when a patch instance is not available, the means for executing the sequence of instructions loads a next subsequent instruction from the sequence of instructions;   otherwise, when a patch instance is available, the means for executing the sequence of instructions determines a patch type from information stored at the address associated with the patch indicator; and   executes one or more instructions in the patch instance.