Circuits for phase-cut analog dimming of solid state light sources

Abstract

Circuits to provide phase-cut analog dimming of solid state light sources are presented. Each circuit comprises an anchoring circuit to communicate with a dimming controller circuit, the anchoring circuit having a proportional direct current (DC) voltage input, a biasing voltage input, a connection to a ground reference, and an output in communication with a dimming controller circuit. The anchoring circuit provides a reference voltage to permit phase cut dimming to be operable at a plurality of line voltages.

What is claimed is: 
     
         1 . An anchoring circuit in communication with a dimming controller circuit, comprising:
 a proportional direct current (DC) voltage input;   a biasing voltage input;   a connection to a ground reference;   a first resistor comprising a first lead and a second lead, wherein the first lead of the first resistor is coupled to a line voltage;   a second resistor comprising a first lead and a second lead, wherein the first lead of the second resistor is coupled to the second lead of the first resistor, and wherein the second lead of the second resistor is coupled to connection to the ground reference;   a diode comprising an anode and a cathode, wherein the anode is coupled to the second lead of the first resistor;   a first capacitor comprising a first lead and a second lead, wherein the first lead of the first capacitor is coupled to the cathode of the diode, and wherein the second lead of the first capacitor is coupled to the connection to the ground reference;   a third resistor comprising a first lead and a second lead, wherein the first lead of the third resistor is coupled to the cathode of the diode;   a fourth resistor comprising a first lead and a second lead, wherein the first lead of the fourth resistor is coupled to the second lead of the third resistor, and wherein the second lead of the fourth resistor is coupled to the connection to the ground reference;   a first transistor comprising a first lead, a second lead, and a third lead, wherein the first lead of the first transistor is coupled to the second lead of the fourth resistor, wherein the third lead of the first transistor is coupled to the connection to the ground reference, and wherein the second lead of the first transistor comprises an output of the anchoring circuit in communication with the dimming controller circuit;   a fifth resistor comprising a first lead and a second lead, wherein the first lead of the fifth resistor is coupled to the second lead of the third resistor;   a second transistor comprising a first lead, a second lead, and a third lead, wherein the first lead of the second transistor is coupled to the second lead of the fourth resistor, wherein the second lead of the second transistor is coupled to the second lead of the third resistor, and wherein the third lead of the second transistor is coupled to the connection to the ground reference;   a third transistor comprising a first lead, a second lead, and a third lead, wherein the first lead of the third transistor is coupled to the second lead of the fifth resistor, and wherein the third lead of the first transistor is coupled to the connection to the ground reference; and   a second capacitor comprising a first lead and a second lead, wherein the first lead of the second capacitor is coupled to the second lead of the first transistor, and the second lead of the second capacitor is capable of being coupled to the dimming controller circuit;   wherein the anchoring circuit provides a reference voltage to permit phase cut dimming to be operable at a plurality of line voltages.   
     
     
         2 . The anchoring circuit of  claim 1 , wherein the first transistor comprises a MOSFET and wherein the first lead of the MOSFET comprises a gate of the MOSFET, the second lead of the MOSFET comprises a drain of the MOSFET, and the third lead of the MOSFET comprises a source of the MOSFET. 
     
     
         3 . The anchoring circuit of  claim 1 , wherein the first transistor comprises a silicon controlled rectifier (SCR) and wherein the first lead of the SCR comprises an anode, the second lead comprises a gate, and the third lead comprises a cathode. 
     
     
         4 . The anchoring circuit of  claim 1 , wherein the second transistor comprises an NPN transistor and wherein the first lead of the NPN transistor comprises a base of the NPN transistor, the second lead of the NPN transistor comprises an emitter of the NPN transistor, and the third lead of the NPN transistor comprises a collector of the NPN transistor. 
     
     
         5 . The anchoring circuit of  claim 1 , wherein the third transistor comprises a MOSFET and wherein the first lead of the MOSFET comprises a gate of the MOSFET, the second lead of the MOSFET comprises a drain of the MOSFET, and the third lead of the MOSFET comprises a source of the MOSFET. 
     
     
         6 . The anchoring circuit of  claim 1 , wherein for a first input voltage, the third transistor is open, the second transistor is closed, and the first transistor is open. 
     
     
         7 . The anchoring circuit of  claim 1 , wherein for a second input voltage, the third transistor is closed, the second transistor is open, and the first transistor is closed. 
     
     
         8 . A phase cut dimming circuit, comprising:
 a dimming controller circuit comprising an input configured to receive a line voltage, a connection to a ground, and an output;   an anchoring circuit in communication with the dimming controller circuit, the anchoring circuit comprising an input, a connection to a ground, and an output in communication with the dimming controller circuit;   wherein the anchoring circuit provides a reference voltage to permit phase cut dimming to be operable at a plurality of line voltages, and wherein the anchoring circuit comprises:
 a first resistor comprising a first lead and a second lead, wherein the first lead of the first resistor is coupled to a line voltage; 
 a second resistor comprising a first lead and a second lead, wherein the first lead of the second resistor is coupled to the second lead of the first resistor, and the second lead of the second resistor is coupled to a ground; 
 a diode comprising an anode and a cathode, wherein the anode is coupled to the second lead of the first resistor; 
 a first capacitor comprising a first lead and a second lead, wherein the first lead of the first capacitor is coupled to the cathode of the diode, and wherein the second lead of the first capacitor is coupled to a ground; 
 a third resistor comprising a first lead and a second lead, wherein the first lead of the third resistor is coupled to the cathode of the diode; 
 a fourth resistor comprising a first lead and a second lead, wherein the first lead of the fourth resistor is coupled to the second lead of the third resistor, and wherein the second lead of the fourth resistor is coupled to a ground; 
 a first transistor comprising a first lead, a second lead, and a third lead, wherein the first lead of the first transistor is coupled to the second lead of the fourth resistor, wherein the third lead of the first transistor is coupled to a ground, and wherein the second lead of the first transistor comprises an output of the anchoring circuit in communication with the dimming controller circuit; 
 a fifth resistor comprising a first lead and a second lead, wherein the first lead of the fifth resistor is coupled to the second lead of the third resistor; 
 a second transistor comprising a first lead, a second lead, and a third lead, wherein the first lead of the second transistor is coupled to the second lead of the fourth resistor, wherein the second lead of the second transistor is coupled to the second lead of the third resistor, and wherein the third lead of the second transistor is coupled to a ground; 
 a third transistor comprising a first lead, a second lead, and a third lead, wherein the first lead of the third transistor is coupled to the second lead of the fifth resistor, and wherein the third lead of the first transistor is coupled to the connection to a ground; and 
 a second capacitor comprising a first lead and a second lead, wherein the first lead of the second capacitor is coupled to the second lead of the first transistor, and the second lead of the second capacitor is capable of being coupled to the dimming controller circuit 
   
     
     
         9 . The phase cut dimming circuit of  claim 8 , wherein the first transistor comprises a MOSFET and wherein the first lead of the MOSFET comprises a gate of the MOSFET, the second lead of the MOSFET comprises a drain of the MOSFET, and the third lead of the MOSFET comprises a source of the MOSFET. 
     
     
         10 . The phase cut dimming circuit of  claim 8 , wherein the dimming controller circuit comprises:
 a controller comprising an input coupled to a center point of a voltage divider circuit, the controller providing an output to couple to a primary side regulated analog flyback converter; and   wherein the voltage divider circuit is coupled between the line voltage and a ground, and wherein the voltage divider circuit comprises:
 a first resistor comprising a first lead coupled to the input of the controller and a second lead coupled to the ground; 
 a second resistor comprising a first lead coupled to the input of the controller and a second lead coupled to the line voltage, and wherein the first lead of the second resistor and the first lead of the first resistor comprise the center point of the voltage divider circuit; and 
 a third resistor comprising a first lead coupled to the center point of the voltage divider circuit and a second lead to couple to an input of the anchoring circuit. 
   
     
     
         11 . The phase cut dimming circuit of  claim 8 , wherein the first transistor comprises a silicon controlled rectifier (SCR) and wherein the first lead of the SCR comprises an anode, the second lead of the SCR comprises a gate, and the third lead of the SCR comprises a cathode. 
     
     
         12 . The phase cut dimming circuit of  claim 8 , wherein the second transistor comprises an NPN transistor and wherein the first lead of the NPN transistor comprises a base of the NPN transistor, the second lead of the NPN transistor comprises an emitter of the NPN transistor, and the third lead of the NPN transistor comprises a collector of the NPN transistor. 
     
     
         13 . The phase cut dimming circuit of  claim 8 , wherein the third transistor comprises a MOSFET and wherein the first lead of the MOSFET comprises a gate of the MOSFET, the second lead of the MOSFET comprises a drain of the MOSFET, and the third lead of the MOSFET comprises a source of the MOSFET. 
     
     
         14 . The phase cut dimming circuit of  claim 8 , wherein for a first input voltage, the third transistor is open, the second transistor is closed, and the first transistor is open. 
     
     
         15 . The phase cut dimming circuit of  claim 8 , wherein for a second input voltage, the third transistor is closed, the second transistor is open, and the first transistor is closed.