Clock generation circuit having deskew function and semiconductor integrated circuit device including same

Abstract

A clock generation circuit having a deskew function and a semiconductor integrated circuit device including the same are provided. The clock generation circuit includes a clock gating circuit configured to gate an input clock signal based on a first waveform signal to generate a first output signal, a flip-flop configured to receive the input clock signal and a second waveform signal and to generate a second output signal, and an OR circuit configured to perform an OR operation on the first output signal and the second output signal to generate an output clock signal having a period which is N times a period of the input clock signal.

1 . A clock generation circuit comprising:
 a clock gating circuit configured to receive a first waveform signal in response to an input clock signal and generate a first output signal;   a flip-flop configured to receive the input clock signal and a second waveform signal and generate a second output signal; and   an OR circuit configured to perform an OR operation on the first output signal and the second output signal to generate an output clock signal having a period which is N times that of a period of the input clock signal, where ‘N’ is a positive real number.   
     
     
         2 . The clock generation circuit of  claim 1 , wherein the clock gating circuit comprises:
 a latch configured to latch the first waveform signal in response to the input clock signal; and   an AND element configured to perform an AND operation on an output signal of the latch and the input clock signal.   
     
     
         3 . The clock generation circuit of  claim 1 , further comprising:
 a waveform generator configured to generate the first waveform signal and the second waveform signal in response to the input clock signal.   
     
     
         4 . The clock generation circuit of  claim 3 , wherein the waveform generator divides a frequency of the input clock signal by N to generate the first and second waveform signals having a period that is N times the period of the input clock signal and having the same duty ratio. 
     
     
         5 . The clock generation circuit of  claim 4 , wherein N is an even number and the clock generation circuit deskews either one of a rising edge and a falling edge of the output clock signal. 
     
     
         6 . The clock generation circuit of  claim 3 , wherein the waveform generator divides a frequency of the input clock signal by N to generate the first and second waveform signals having a period that is N times the period of the input clock signal and having different duty ratios. 
     
     
         7 . The clock generation circuit of  claim 6 , wherein N is an odd number and the clock generation circuit deskews both of a rising edge and a falling edge of the output clock signal. 
     
     
         8 . The clock generation circuit of  claim 1 , wherein the first and second waveform signals are an inverted version of the second output signal. 
     
     
         9 . The clock generation circuit of  claim 8 , wherein the flip-flop comprises:
 a clock terminal configured to receive the input clock signal;   an input terminal configured to receive the second waveform signal;   a positive output terminal configured to output the second output signal; and   a negative output terminal configured to output an inverted version of the second output signal, and   the output signal of the negative output signal is provided as the first and second waveform signals.   
     
     
         10 . The clock generation circuit of  claim 8 , wherein the clock generation circuit passes and outputs the input clock signal as the output clock signal in response to a reset signal during a reset period. 
     
     
         11 . The clock generation circuit of  claim 1 , further comprising:
 a second flip-flop configured to delay a clock stop request signal to generate a clock stop response signal; and   a logic operation element configured to generate the first and second waveform signals based on the clock stop request signal.   
     
     
         12 . A semiconductor integrated circuit device comprising:
 a clock generation circuit configured to receive an input clock signal and generate an output clock signal having a period N times that of a period of the input clock signal and having skew of at least one of a rising edge and a falling edge reduced, where N is a positive real number; and   a logic circuit configured to receive the output clock signal,   wherein the clock generation circuit comprises:   a clock gating circuit configured to receive a first waveform signal in response to the input clock signal and generate a first output signal;   a first flip-flop configured to delay a second waveform signal in response to the input clock signal to generate a second output signal; and   an OR circuit configured to perform an OR operation on the first output signal and the second output signal to generate the output clock signal.   
     
     
         13 . The semiconductor integrated circuit device of  claim 12 , wherein the clock gating circuit comprises:
 a latch configured to latch the first waveform signal in response to the input clock signal; and   an AND element configured to perform an AND operation on an output signal of the latch and the input clock signal.   
     
     
         14 - 18 . (canceled) 
     
     
         19 . The semiconductor integrated circuit device of  claim 12 , wherein the first flip-flop comprises:
 a positive output terminal configured to output the second output signal; and   a negative output terminal configured to output an inverted signal of the second output signal, and   the first and second waveform signals are based on a signal of the negative output terminal of the first flip-flop.   
     
     
         20 . The semiconductor integrated circuit device of  claim 19 , wherein the clock generation circuit further comprises:
 a second flip-flop configured to delay a clock stop request signal to generate a clock stop response signal; and   a logic operation element configured to perform an AND operation on an inverted signal of the clock stop request signal and the signal of the negative output terminal to generate the first and second waveform signals.   
     
     
         21 - 25 . (canceled) 
     
     
         26 . A clock generation circuit comprising:
 a waveform generator configured to generate a first waveform signal and a second waveform signal from an input clock signal;   a buffer configured to receive the input clock signal and generate a buffered input clock signal;   a clock gating circuit configured to receive the first waveform signal, gate the first waveform signal in response to the buffered input clock signal, and generate a first output signal;   a flip-flop configured to receive the buffered input clock signal and the second waveform signal and generate a second output signal; and   an OR circuit configured to perform an OR operation on the first output signal and the second output signal to generate an output clock signal having a period that is N times that of the period of the input clock signal, where ‘N’ is a positive real number.   
     
     
         27 . The clock generation circuit of  claim 26 , wherein the clock gating circuit comprises:
 a latch configured to latch the first waveform signal in response to the buffered input clock signal; and   an AND element configured to perform an AND operation on an output signal of the latch and the buffered input clock signal.   
     
     
         28 . The clock generation circuit of  claim 26 , wherein the waveform generator divides a frequency of the input clock signal by N to generate the first and second waveform signals having a period that is N times the period of the input clock signal and having the same duty ratio. 
     
     
         29 . The clock generation circuit of  claim 28 , wherein N is an even number and the clock generation circuit deskews either one of a rising edge and a falling edge of the output clock signal. 
     
     
         30 . The clock generation circuit of  claim 26 , wherein the waveform generator divides a frequency of the input clock signal by N to generate the first and second waveform signals having a period that is N times the period of the input clock signal and having different duty ratios. 
     
     
         31 . (canceled)