Integration of air-sensitive two-dimensional materials on arbitrary substrates for the manufacturing of electronic devices

Abstract

A field-effect transistor and method for fabricating such a field-effect transistor that utilizes an air-sensitive two-dimensional material (e.g., silicene). A film of air-sensitive two-dimensional material is deposited on a crystallized metallic (e.g., Ag) thin film on a substrate (e.g., mica substrate). A capping layer of insulating material (e.g., aluminum oxide) is deposited on the air-sensitive two-dimensional material. The substrate is detached from the metallic thin film/air-sensitive two-dimensional material/insulating material stack structure. The metallic thin film/air-sensitive two-dimensional material/insulating material stack structure is then flipped. The flipped metallic thin film/air-sensitive two-dimensional material/insulating material stack structure is attached to a device substrate followed by having the metallic thin film etched to form contact electrodes. In this manner, the pristine properties of air-sensitive two-dimensional materials are preserved from degradation when exposed to air. Furthermore, this new technique allows safe transfer and device fabrication of air-sensitive two-dimensional materials with a low material and process cost.

1 . A method for fabricating a field-effect transistor, the method comprising:
 depositing a film of air-sensitive two-dimensional material on a crystallized metallic thin film on a substrate;   depositing a capping layer of insulating material on said air-sensitive two-dimensional material;   detaching said substrate from said metallic thin film/air-sensitive two-dimensional material/insulating material stack structure;   flipping said metallic thin film/air-sensitive two-dimensional material/insulating material stack structure;   attaching said flipped metallic thin film/air-sensitive two-dimensional material/insulating material stack structure to a device substrate; and   etching said metallic thin film forming contact electrodes.   
     
     
         2 . The method as recited in  claim 1 , wherein said air-sensitive two-dimensional material comprises a two-dimensional material of an element from Group IV or Group V in a periodic table. 
     
     
         3 . The method as recited in  claim 1 , wherein said air-sensitive two-dimensional material comprises one of the following: silicene, germanene, stanene and phosphorene. 
     
     
         4 . The method as recited in  claim 1 , wherein said metallic thin film comprises silver. 
     
     
         5 . The method as recited in  claim 1 , wherein said substrate comprises mica. 
     
     
         6 . The method as recited in  claim 1 , wherein said insulating material comprises aluminum oxide. 
     
     
         7 . The method as recited in  claim 1 , wherein said device substrate comprises a dielectric layer on a substrate. 
     
     
         8 . The method as recited in  claim 7 , wherein said dielectric layer comprises silicon dioxide and said substrate comprises silicon. 
     
     
         9 . The method as recited in  claim 1 , wherein said contact electrodes comprises a drain and a source contact. 
     
     
         10 . The method as recited in  claim 1 , wherein said film of air-sensitive two-dimensional material was deposited on said crystallized metallic thin film from a heated crucible in a built-in evaporator at a temperature of approximately 250-270° C. and a rate of approximately 2-6×10 −2  monolayers per minute. 
     
     
         11 . The method as recited in  claim 1 , wherein said insulating material was deposited on said film of air-sensitive two-dimensional material using a reactive molecular beam. 
     
     
         12 . The method as recited in  claim 1 , wherein said insulating material comprises aluminum oxide, wherein said aluminum oxide has a thickness of approximately between 3 and 50 nanometers. 
     
     
         13 . The method as recited in  claim 1 , wherein said substrate is detached from said metallic thin film/air-sensitive two-dimensional material/insulating material stack structure by initiating a gap at an edge between said metallic thin film and said substrate. 
     
     
         14 . The method as recited in  claim 1 , wherein a blade is used to initiate said gap at said edge between said metallic thin film and said substrate. 
     
     
         15 . The method as recited in  claim 1 , wherein a potassium iodide and iodine-based etchant is used to etch said metallic thin film to form said contact electrodes. 
     
     
         16 . A field-effect transistor, comprising:
 a substrate;   a dielectric layer positioned on said substrate;   a layer of insulating material positioned on said dielectric layer;   a layer of air-sensitive two-dimensional material positioned on said insulating layer;   a channel of said air-sensitive two-dimensional material defined atop said insulating layer;   a layer of metallic film positioned on said layer of air-sensitive two-dimensional material;   a drain contact defined in said metallic film; and   a source contact defined in said metallic film.   
     
     
         17 . The field-effect transistor as recited in  claim 16 , wherein said air-sensitive two-dimensional material comprises a two-dimensional material of an element from Group IV or Group V in a periodic table. 
     
     
         18 . The field-effect transistor as recited in  claim 16 , wherein said air-sensitive two-dimensional material comprises one of the following: silicene, germanene, stanene and phosphorene. 
     
     
         19 . The field-effect transistor as recited in  claim 16 , wherein said metallic thin film comprises silver. 
     
     
         20 . The field-effect transistor as recited in  claim 16 , wherein said substrate comprises mica. 
     
     
         21 . The field-effect transistor as recited in  claim 16 , wherein said insulating material comprises aluminum oxide. 
     
     
         22 . The field-effect transistor as recited in  claim 21 , wherein said aluminum oxide has a thickness of approximately between 3 and 50 nanometers. 
     
     
         23 . The field-effect transistor as recited in  claim 16 , wherein said dielectric layer comprises silicon dioxide which is positioned on said substrate comprising silicon. 
     
     
         24 . The field-effect transistor as recited in  claim 23 , wherein a thickness of said layer of silicon dioxide and said silicon substrate is approximately 500 micrometers. 
     
     
         25 . The field-effect transistor as recited in  claim 23 , wherein a thickness of said layer of said silicon dioxide is approximately between 5 and 500 nanometers, wherein said silicon substrate is p-type. 
     
     
         26 . The field-effect transistor as recited in  claim 16 , wherein said channel of air-sensitive two-dimensional material has a thickness of approximately between 0.3 and 1 nanometer. 
     
     
         27 . The field-effect transistor as recited in  claim 16 , wherein said drain and source contacts have a thickness of approximately between 50 and 500 nanometers.