US2017117383A1PendingUtilityA1

Method for forming a semiconductor device

Assignee: INFINEON TECHNOLOGIES AGPriority: Dec 10, 2013Filed: Jan 5, 2017Published: Apr 27, 2017
Est. expiryDec 10, 2033(~7.4 yrs left)· nominal 20-yr term from priority
H10P 50/642H10P 14/6324H10P 14/6309H10P 14/6304H10P 14/683H10W 20/076H10W 20/023H10W 20/0234H10W 20/0242H10D 8/00H01L 21/02118H01L 21/02238H01L 29/7811H01L 29/0661H01L 21/76898H01L 29/6634H01L 29/66348H01L 21/76831H01L 29/7397H01L 21/30604H01L 29/66333H01L 21/02258H01L 29/66734H10D 64/111H10D 62/111H10D 62/104H10D 30/665H10D 30/0297H10D 30/0291H10D 12/481H10D 12/461H10D 12/038H10D 12/035H10D 12/032
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Claims

Abstract

A method for forming a semiconductor device includes forming an electrical structure at a main surface of a semiconductor substrate and carrying out an anodic oxidation of a back side surface region of a back side surface of the semiconductor substrate to form an oxide layer at the back side surface of the semiconductor substrate. Additionally, the method includes connecting a carrier substrate to the oxide layer and processing a back side of the semiconductor substrate.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A method for forming a semiconductor device, the method comprising:
 forming an electrically conductive layer above a main surface of a semiconductor substrate;   carrying out an anodic oxidation of a surface of the electrically conductive layer to form an oxide layer at the surface of the electrically conductive layer;   connecting a carrier substrate to the oxide layer; and   processing a back side of the semiconductor substrate.   
     
     
         2 . The method according to  claim 1 , wherein a surface of the oxide layer comprises at least one uneven area causing a gap between the carrier substrate and the oxide layer, wherein the method further comprises removing the carrier wafer by inserting acid at least into the gap. 
     
     
         3 . A method for forming a semiconductor device, the method comprising:
 forming an edge termination trench extending from a main surface of a semiconductor substrate towards an opposite back side of the semiconductor substrate, wherein the trench surrounds an active area of the semiconductor device; and   carrying out an anodic oxidation of a surface of the edge termination trench to form an oxide layer at least at a wall of the edge termination trench.   
     
     
         4 . The method according to  claim 3 , further comprising at least partly filling the edge termination trench with a polymer. 
     
     
         5 . The method according to  claim 3 , wherein processes for forming structures associated with the semiconductor substrate carried out after the anodic oxidation comprise process temperatures below 650° C. 
     
     
         6 . The method according to  claim 3 , further comprising forming at least one field effect transistor structure at the main surface of the semiconductor substrate. 
     
     
         7 . The method according to  claim 3 , wherein at least one semiconductor structure of the semiconductor device comprises a blocking voltage of more than 10V. 
     
     
         8 . A method for forming a semiconductor device, the method comprising:
 forming an electrical structure at a main surface of a semiconductor substrate; and   carrying out an anodic oxidation of a back side surface region of a back side surface of the semiconductor substrate to form an oxide layer at the back side surface of the semiconductor substrate.   
     
     
         9 . The method according to  claim 8 , comprising forming a p-doped region adjacent to an n-doped region at the back side surface of the semiconductor substrate, wherein the oxide layer in a first portion of the back side surface extending along the n-doped region has a greater thickness than the oxide layer in a second portion of the back side surface extending along the p-doped region. 
     
     
         10 . The method according to  claim 8 , further comprising removing the oxide layer at a back side emitter region and forming an emitter doping region of an insulated gate bipolar transistor within the semiconductor substrate at the back side emitter region arranged at the back side surface of the semiconductor substrate. 
     
     
         11 . The method according to  claim 10 , further comprising implanting dopants of a first conductivity type with an implant energy higher than an implant energy used for forming the emitter doping region to generate a first conductivity type doping layer within a region covered by the oxide layer and within the back side emitter region, where the first conductivity type doping layer extends to a first average depth within the back side emitter region and to a second average depth within the region covered by the oxide layer, wherein the first depth is larger than the second depth. 
     
     
         12 . The method according to  claim 10 , wherein the emitter doping region comprises a first conductivity type and an adjacent part of the semiconductor substrate comprises a second conductivity type. 
     
     
         13 . The method according to  claim 8 , further comprising forming a field effect transistor structure at the back side of the semiconductor substrate, wherein the oxide layer forms a gate oxide of the field effect transistor structure at the back side. 
     
     
         14 . The method according to  claim 8 , further comprising forming a trench extending from the back side surface to a part of the electrical structure at the main side of the semiconductor substrate, wherein the oxide layer formed during the anodic oxidation covers at least a wall of the trench, wherein the electrical structure at the main surface is a doping region of a diode or a transistor, a gate of a transistor or a metallization of a diode, a transistor, a resistor, a capacitor or an inductor. 
     
     
         15 . The method according to  claim 8 , wherein the oxide layer is formed with a gradient by a variation of the magnitude of the p-doping at the back side surface of the semiconductor surface.

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