Transistor structure with reduced parasitic "side wall" characteristics

Abstract

A MOS transistor structure for matched operation in weak-inversion or sub-threshold range (e.g. input-pair of operational amplifier, comparator, and/or current-mirror) is disclosed. The transistor structure may include a well region of any impurity type in a substrate (SOI is included). The well-region can even be represented by the substrate itself. At least one transistor is located in the well region, whereby the active channel-region of the transistor is independent from lateral isolation interfaces between GOX (gate oxide) and FOX (field oxide; including STI-shallow trench isolation).

What is claimed is: 
     
         1 . At least one field effect transistor comprising:
 a substrate;   a gate dielectric layer on the substrate; and   an isolation layer in the substrate surrounding the gate dielectric layer.   
     
     
         2 . The at least one field effect transistor of  claim 1 , further comprising:
 a well region of a first impurity type in the substrate; and   at least one transistor gate formed at least partially on the well region, a portion of the well region comprising a least one transistor channel;   wherein the gate dielectric layer is arranged between the at least one transistor gate and the at least one transistor channel.   
     
     
         3 . The at least one field effect transistor of  claim 2 , further comprising:
 a ring structure of the first impurity type arranged in the substrate between the well region and the isolation layer;   wherein a concentration of the first impurity type in the ring structure is higher than a concentration of the first impurity type in the well region.   
     
     
         4 . The at least one field effect transistor of  claim 3 ,
 wherein a lateral extension of the gate dielectric layer is bounded by the ring structure.   
     
     
         5 . The at least one field effect transistor of  claim 2 , further comprising:
 a drain region in the well region and a plurality of source regions at least partially in the well region, said source regions being arranged around the at least one transistor gate.   
     
     
         6 . The at least one field effect transistor of  claim 5 ,
 wherein the plurality of source regions comprise four source regions arranged around the perimeter of the drain region in a substantially cross-shaped configuration; and   wherein the well region comprises four transistor channels, one channel formed between each source region and a corresponding portion of the drain region.   
     
     
         7 . The at least one field effect transistor of  claim 5 ,
 wherein the plurality of source regions comprise eight source regions arranged around the perimeter of the drain diffusion region in a substantially octagonal configuration; and   wherein the well region comprises eight transistor channels, one channel formed between each source region and a corresponding portion of the drain region.   
     
     
         8 . The at least one field effect transistor of  claim 5 ,
 wherein the drain region comprises a substantially circular structure; and   wherein the plurality of source regions comprise a substantially annular structure concentrically arranged with the drain region.   
     
     
         9 . The at least one field effect transistor of  claim 8 ,
 wherein the gate electrode comprises an annular structure situated concentrically with the drain region and a planar section extending from the annular structure over the drain region and the plurality of source regions.   
     
     
         10 . The at least one field effect transistor of  claim 1 ,
 wherein the first impurity type comprises a p-type dopant and a second impurity type comprises an n-type dopant; or   wherein the first impurity type comprises a n-type dopant and a second impurity type comprises an p-type dopant.