One-time programmable memory cell capable of reducing leakage current and preventing slow bit response, and method for programming a memory array comprising the same

Abstract

A one time programmable (OTP) memory cell includes a select gate transistor, a following gate transistor, and an antifuse varactor. The select gate transistor has a first gate terminal, a first drain terminal and a first source terminal. The following gate transistor has a second gate terminal, a second drain terminal and a second source terminal coupled to the first drain terminal. The antifuse varactor has a third gate terminal, a third drain terminal, and a third source terminal coupled to the second drain terminal. The select gate transistor, the following gate transistor, and the antifuse varactor are formed on a substrate structure.

What is claimed is: 
     
         1 . A one time programmable (OTP) memory cell, comprising:
 a substrate structure;   a select gate transistor formed on the substrate structure, the select gate transistor having a first gate terminal, a first drain terminal, and a first source terminal;   a following gate transistor formed on the substrate structure, the following gate transistor having a second gate terminal, a second drain terminal, and a second source terminal coupled to the first drain terminal; and   an antifuse varactor formed on the substrate structure, the antifuse varactor having a third gate terminal, a third drain terminal, and a third source terminal coupled to the second drain terminal.   
     
     
         2 . The OTP memory cell of  claim 1 , wherein the first gate terminal, the second gate terminal and the third gate terminal are formed on a first gate oxide layer with a same first thickness. 
     
     
         3 . The OTP memory cell of  claim 1 , wherein the antifuse varactor further has a third source/drain extension area coupled with the third drain terminal and the third source terminal for shorting the third drain terminal and the third source terminal. 
     
     
         4 . The OTP memory cell of  claim 3 , wherein the select gate transistor further has two first source/drain extension areas respectively coupled to the first drain terminal and the first source terminal, and the following gate transistor further has two second source/drain extension areas respectively coupled to the second drain terminal and the second source terminal. 
     
     
         5 . The OTP memory cell of  claim 1 , wherein the substrate structure is a P well over a silicon substrate, and all source terminals and drain terminals are formed by an epitaxial silicon phosphorous (SiP) or silicon carbide (SiC) process. 
     
     
         6 . A one time programmable (OTP) memory cell, comprising:
 a substrate structure;   a select gate transistor formed on the substrate structure, the select gate transistor having a first gate terminal, a first drain terminal, and a first source terminal;   a following gate transistor formed on the substrate structure, the following gate transistor having a second gate terminal, a second drain terminal, and a second source terminal coupled to the first drain terminal; and   an antifuse varactor formed on the substrate structure, the antifuse varactor having a third gate terminal, and a third source terminal coupled to the second drain terminal;   wherein a part of the third gate terminal is formed above a shallow trench insulation area.   
     
     
         7 . The OTP memory cell of  claim 6 , wherein the first gate terminal, the second gate terminal and the third gate terminal are formed on a first gate oxide layer with a same first thickness. 
     
     
         8 . The OTP memory cell of  claim 6 , wherein the antifuse varactor further has a third source/drain extension area coupled to the third source terminal. 
     
     
         9 . The OTP memory cell of  claim 8 , wherein the select gate transistor further has two first source/drain extension areas respectively coupled to the first drain terminal and the first source terminal, and the following gate transistor further has two second source/drain extension areas respectively coupled to the second drain terminal and the second source terminal. 
     
     
         10 . The OTP memory cell of  claim 6 , wherein the substrate structure is a P well over a silicon substrate, and all source terminals and drain terminals are formed by an epitaxial silicon phosphorous (SiP) or silicon carbide (SiC) process.