Semiconductor package with integrated die paddles for power stage

Abstract

In one implementation, a semiconductor package includes a first conductive carrier including a first die paddle of the semiconductor package, and a control transistor having a drain attached to the first die paddle. The semiconductor package also includes a second conductive carrier attached to the first conductive carrier and including a second die paddle of the semiconductor package, and a sync transistor having a drain attached to the second die paddle. The second die paddle couples a source of the control transistor to the drain of the sync transistor.

1 - 10 . (canceled) 
     
     
         11 . A method for fabricating a semiconductor package, said method comprising:
 providing a first conductive carrier including a first die paddle;   attaching a drain of a control transistor to said first die paddle;   attaching a second conductive carrier to said first conductive carrier, said second conductive carrier including a second die paddle;   attaching a drain of a sync transistor to said second die paddle;   utilizing said second die paddle to couple a source of said control transistor to said drain of said sync transistor.   
     
     
         12 . The method of  claim 11 , wherein said second die paddle is configured as an integrated heat spreader for said semiconductor package. 
     
     
         13 . The method of  claim 11 , wherein said control transistor and said sync transistor form a power switching stage of a voltage converter. 
     
     
         14 . The method of  claim 13 , wherein said second die paddle provides a switch node of said power switching stage. 
     
     
         15 . The method of  claim 11 , wherein said first conductive carrier has a reduced thickness. 
     
     
         16 . The method of  claim 11 , wherein said first conductive carrier comprises at least a portion of a partially etched lead frame. 
     
     
         17 . The method of  claim 16 , wherein said partially etched lead frame is substantially half-etched. 
     
     
         18 . The method of  claim 11 , wherein said control transistor and said sync transistor comprise silicon field-effect transistors (FETs). 
     
     
         19 . The method of  claim 11 , wherein said control transistor and said sync transistor comprise III-Nitride high electron mobility transistors (HEMTs). 
     
     
         20 . The method of  claim 11 , wherein said second conductive carrier is configured to connect said first conductive carrier, said control transistor, and said sync transistor to a mounting surface for said semiconductor package.