Integrated circuit and process thereof

Abstract

An integrated circuit process includes the following steps. A substrate including a first area and a second area is provided. A plurality of line patterns cover the substrate of the first area, and a sacrificial line pattern covers the substrate of the second area, wherein these line patterns separate from and are orthogonal to the sacrificial line pattern. The present invention also provides an integrated circuit formed by said process. A substrate includes a first area and a second area; a plurality of line patterns cover the substrate of the first area; a slot pattern is in the substrate of the second area, wherein these line patterns are orthogonal to the slot pattern. Additionally, a plurality of line patterns cover the substrate; a sacrificial line pattern is at ends of the line patterns, wherein these line patterns separate from and are orthogonal to the sacrificial line pattern.

1 . An integrated circuit process, comprising:
 providing a substrate comprising a first area and a second area; and   forming a plurality of line patterns covering the substrate of the first area, and a sacrificial line pattern covering the substrate of the second area, wherein the line patterns are separated from the sacrificial line pattern, the line patterns are orthogonal to the sacrificial line pattern, and the sacrificial line pattern has a minimum width larger than a minimum width of the line patterns.   
     
     
         2 . The integrated circuit process according to  claim 1 , wherein the first area comprises a dense area, the second area comprises an isolated area, and the dense area is right next to the isolated area. 
     
     
         3 . (canceled) 
     
     
         4 . The integrated circuit process according to  claim 1 , wherein the line patterns and the sacrificial line pattern comprise common material. 
     
     
         5 . The integrated circuit process according to  claim 4 , wherein the line patterns and the sacrificial line pattern are formed by one same process. 
     
     
         6 . The integrated circuit process according to  claim 1 , further comprising:
 performing a pattern cutting process to remove the sacrificial line pattern and end parts of the line patterns after the line patterns and the sacrificial line pattern are formed.   
     
     
         7 . The integrated circuit process according to  claim 6 , wherein the step of performing the pattern cutting process comprises:
 forming a patterned photoresist to cover the line patterns, the sacrificial line pattern and the substrate;   transferring the pattern of the patterned photoresist to remove the sacrificial line pattern and the end parts of the line patterns; and   removing the patterned photoresist.   
     
     
         8 . The integrated circuit process according to  claim 7 , further comprising:
 entirely covering an optical dispersive layer (ODL) or/and a silicon-containing hard mask bottom anti-reflection coating (SHB) layer on the line patterns, the sacrificial line pattern and the substrate before the patterned photoresist is formed.   
     
     
         9 . The integrated circuit process according to  claim 7 , wherein the integrated circuit process comprises: entirely covering an optical dispersive layer (ODL) and a silicon-containing hard mask bottom anti-reflection coating (SHB) layer on the line patterns, the sacrificial line pattern and the substrate before the patterned photoresist is formed, and the step of performing the pattern cutting process comprises:
 transferring the pattern of the patterned photoresist to the optical dispersive layer (ODL) and the silicon-containing hard mask bottom anti-reflection coating (SHB) layer; and   transferring the pattern of the optical dispersive layer (ODL) and the silicon-containing hard mask bottom anti-reflection coating (SHB) layer to remove the sacrificial line pattern and the end parts of the line patterns.   
     
     
         10 . The integrated circuit process according to  claim 1 , wherein the line patterns comprise gate patterns, fin patterns, spacer patterns or mask patterns. 
     
     
         11 . The integrated circuit process according to  claim 10 , wherein the line patterns are gate patterns comprising polysilicon patterns or amorphous silicon patterns. 
     
     
         12 . The integrated circuit process according to  claim 10 , wherein the line patterns are mask patterns comprising nitride over oxide layer patterns. 
     
     
         13 - 20 . (canceled) 
     
     
         21 . An integrated circuit process, comprising:
 providing a substrate comprising a first area and a second area; and   forming a plurality of line patterns covering the substrate of the first area, and a sacrificial line pattern being a rectangular line pattern covering the substrate of the second area, wherein the line patterns separate from the sacrificial line pattern, and the line patterns are orthogonal to the whole sacrificial line pattern.   
     
     
         22 . An integrated circuit process, comprising:
 providing a substrate comprising a first area and a second area; and   forming a plurality of line patterns along at x-direction covering the substrate of the first area, and a sacrificial line pattern along at y-direction covering the substrate of the second area, wherein the sacrificial line pattern exceeds from the line patterns at y-direction, the line patterns separate from the sacrificial line pattern, and the line patterns are orthogonal to the sacrificial line pattern.