Semiconductor package and manufacturing method thereof

Abstract

A semiconductor package includes a substrate, at lest one support, a cover, and a plate. The substrate has at least one light sensor or thermal sensor, a first surface, and a second surface opposite to the first surface. The light sensor or the thermal sensor is disposed on the first surface. The second surface has an opening to expose the light sensor (or the thermal sensor). The support is disposed on the first surface. The cover is disposed on the support, such that the cover is above the light sensor (or the thermal sensor) to form a first space between the cover and the light sensor (or the thermal sensor). The plate is placed on the second surface to cover the opening, such that a second space is formed between the plate and the light sensor (or the thermal sensor).

What is claimed is: 
     
         1 . A semiconductor package, comprising:
 a substrate having at least one light sensor or at least one thermal sensor, a first surface, and a second surface opposite to the first surface, wherein the first surface has a recess and an electrical connecting pad, and the at least one light sensor or the at least one thermal sensor is disposed on the first surface and covers the recess;   at least one support disposed on the first surface of the substrate;   a cover located on the at least one support, such that a space is formed between the cover and the at least one light sensor or between the cover and the at least one thermal sensor;   an isolation layer located on the second surface of the substrate; and   a redistribution layer located on the isolation layer and electrically connected to the electrical connecting pad.   
     
     
         2 . The semiconductor package of  claim 1 , further comprising:
 a protection layer located on the isolation layer and the redistribution layer, wherein the protection layer has an opening hole for exposing a portion of a surface of the redistribution layer.   
     
     
         3 . The semiconductor package of  claim 2 , further comprising:
 a conductive protrusion located on the redistribution layer in the opening hole.   
     
     
         4 . The semiconductor package of  claim 1 , wherein the substrate has a wall surface adjacent to the electrical connecting pad and the second surface, and the isolation layer is located on the wall surface. 
     
     
         5 . The semiconductor package of  claim 4 , wherein an obtuse angle is included between the wall surface and the second surface. 
     
     
         6 . The semiconductor package of  claim 4 , wherein the wall surface is perpendicular to the second surface and the electrical connecting pad. 
     
     
         7 . A manufacturing method of a semiconductor package, comprising:
 providing a wafer that has at least one light sensor or at least one thermal sensor, a first surface, and a second surface opposite to the first surface, wherein the at least one light sensor or the at least one thermal sensor is disposed on the first surface and covers a recess of the first surface;   disposing a cover on the first surface of the wafer by at least one support, such that the cover is above the at least one light sensor or the at least one thermal sensor, and a space is formed between the cover and the at least one light sensor or between the cover and the at least one thermal sensor;   forming a through hole in the second surface of the wafer for exposing the at least one support and an electrical connecting pad of the wafer;   forming an isolation layer on the second surface of the wafer and a wall surface that surrounds the through hole; and   forming a redistribution layer on the isolation layer, wherein the redistribution layer is electrically connected to the electrical connecting pad.   
     
     
         8 . The manufacturing method of the semiconductor package of  claim 7 , forming the isolation layer on the second surface of the wafer and the wall surface that surrounds the through hole further comprising:
 using the isolation layer to cover the through hole; and   forming a notch in the isolation layer in the through hole, such that the isolation layer is located on the wall surface of the wafer surrounding the through hole.   
     
     
         9 . The manufacturing method of the semiconductor package of  claim 7 , further comprising:
 forming a protection layer on the isolation layer and the redistribution layer; and   patterning the protection layer to form an opening hole for exposing the redistribution layer.   
     
     
         10 . The manufacturing method of the semiconductor package of  claim 9 , further comprising:
 forming a conductive protrusion on the redistribution layer in the opening hole.   
     
     
         11 . The manufacturing method of the semiconductor package of  claim 7 , further comprising:
 vertically dicing the cover, the at least one support, and the wafer along the through hole.