US2017110586A1PendingUtilityA1

Semiconductor device and method for manufacturing the same

Assignee: SEMICONDUCTOR ENERGY LABPriority: Feb 29, 2012Filed: Dec 29, 2016Published: Apr 20, 2017
Est. expiryFeb 29, 2032(~5.6 yrs left)· nominal 20-yr term from priority
H10P 14/3456H10P 14/3434H10P 14/22H01L 29/7869H01L 21/02595H01L 21/02565H01L 29/78603H01L 29/66969H01L 21/02631H01L 29/24H01L 29/04H10D 99/00H10D 62/80H10D 62/40H10D 30/6758H10D 30/031H10D 30/6755
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Claims

Abstract

An oxide semiconductor layer is formed, a gate insulating layer is formed over the oxide semiconductor layer, a gate electrode layer is formed to overlap with the oxide semiconductor layer with the gate insulating layer interposed therebetween, a first insulating layer is formed to cover the gate insulating layer and the gate electrode layer, an impurity element is introduced through the insulating layer to form a pair of impurity regions in the oxide semiconductor layer, a second insulating layer is formed over the first insulating layer, the first insulating layer and the second insulating layer are anisotropically etched to form a sidewall insulating layer in contact with a side surface of the gate electrode layer, and a source electrode layer and a drain electrode layer in contact with the pair of impurity regions are formed.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A semiconductor device comprising:
 an oxide semiconductor layer, the oxide semiconductor layer including a pair of impurity regions containing an impurity element and a channel formation region between the pair of impurity regions;   a gate electrode layer over the oxide semiconductor layer;   a sidewall insulating layer being in contact with a side surface of the gate electrode layer and containing the impurity element;   a source electrode layer in contact with one of the pair of impurity regions; and   a drain electrode layer in contact with the other of the pair of impurity regions,   wherein in the pair of impurity regions, an impurity concentration in a region in contact with the source electrode layer or the drain electrode layer is higher than an impurity concentration in a region overlapping with the sidewall insulating layer.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein the oxide semiconductor layer includes a microcrystal. 
     
     
         3 . The semiconductor device according to  claim 1 , wherein the oxide semiconductor layer includes indium, gallium, and zinc. 
     
     
         4 . The semiconductor device according to  claim 1 , wherein an oxide vacancy is formed in the pair of impurity regions. 
     
     
         5 . The semiconductor device according to  claim 1 , wherein the sidewall insulating layer includes the impurity element. 
     
     
         6 . The semiconductor device according to  claim 1 , wherein a thickness of the second insulating layer is larger than a thickness of the first insulating layer. 
     
     
         7 . The semiconductor device according to  claim 1 , further comprising a base insulating layer in contact with the oxide semiconductor layer,
 wherein the base insulating layer includes a region containing oxygen in excess of a stoichiometric composition.

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