Semiconductor devices having hybrid stacking structures and methods of fabricating the same

Abstract

A semiconductor device having a chip stack and an interconnection terminal is provided. The chip stack includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip stacked on each other. The interconnection terminal is electrically coupled to the chip stack. The first semiconductor chip includes a first front surface and a first backside surface. The second semiconductor chip includes a second front surface, a second backside surface, a second circuit layer and a through-electrode which is electrically coupled to the second circuit layer and penetrates the second semiconductor chip. The third semiconductor chip includes a third front surface, a third backside surface opposite to the third front surface and a third circuit layer adjacent to the third front surface. The first front surface and the second front surface face each other. The third front surface and the second backside surface face each other.

What is claimed is: 
     
         1 . A method of fabricating a semiconductor device, the method comprising:
 stacking a first semiconductor chip and a second semiconductor chip,
 wherein the first semiconductor chip includes a first front surface, a first backside surface opposite to the first front surface and a first circuit layer adjacent to the first front surface, and 
 the second semiconductor chip includes a second front surface, a second backside surface opposite to the second front surface, a second circuit layer adjacent to the second front surface and a through-electrode which is electrically coupled to the second circuit layer and spaced apart from the second backside surface, and 
 wherein the first front surface and the second front surface face each other; 
   grinding the second backside surface to expose the through-electrode of the second semiconductor chip;   grinding the first backside surface to reduce the first semiconductor chip to a first reduced thickness;   stacking a third semiconductor chip on the grinded second backside surface,
 wherein the third semiconductor chip includes a third front surface, a third backside surface opposite to the third front surface and a third circuit layer adjacent to the third front surface, 
 wherein the third front surface and the grinded second backside surface face each other; 
   grinding the third backside surface to reduce a thickness of the third semiconductor chip; and   grinding the grinded first backside surface to reduce the first semiconductor chip to a second reduced thickness, wherein the second reduced thickness is smaller than the first reduced thickness,   wherein the second semiconductor chip comprises the through-electrode partially penetrating the second semiconductor chip,   wherein the grinding of the first backside surface is performed before the stacking of the third semiconductor chip, and   wherein the grinding of the grinded first backside surface is performed after the stacking of the third semiconductor chip.