Nonvolatile semiconductor memory device

Abstract

A semiconductor memory device includes a memory cell array, a sense amplifier, a register, a controller. The memory cell array includes a memory cell. The sense amplifier connects to the bit line. The register holds write data, and a write voltage. The controller outputs a busy signal. The controller causes the register to hold the write data and the write voltage upon receiving the first command, and resumes the write operation based on the write data and the write voltage held in the register upon receiving the resumption command.

What is claimed is: 
     
         1 . A nonvolatile semiconductor memory device comprising:
 a word line connected to a memory cell array; and   a controller configured to be capable of applying a voltage to the word line, perform a write operation upon reception of a write command, and output a busy signal representing that the write operation is progressing,   wherein the write operation includes a first phase, a second phase, and a third phase that are executed in the order given,   the controller performs a first verify operation after applying a first program voltage to the word line during the first phase; applies a second program voltage to the word line during the second phase; interrupts the write operation if an interruption command is received during the second phase; resumes the write operation if a resumption command is received after the interruption; applies a third program voltage to the word line during the third phase after the resumption; and the second program voltage is higher than the first program voltage, and the third program voltage is higher than the second program voltage.   
     
     
         2 . The device of  claim 1 , wherein the controller outputs a ready signal after the interruption, and outputs a busy signal after resumption of the write signal. 
     
     
         3 . The device of  claim 2 , wherein the controller performs a read operation if a read command is received after the interruption, and is capable of receiving the resumption command after completion of the read operation. 
     
     
         4 . The device of  claim 3 , wherein the controller outputs a busy signal during the read operation. 
     
     
         5 . The device of  claim 1 , wherein the controller performs a second verify operation before applying the third program voltage to the word line during the third phase if the resumption command is received. 
     
     
         6 . The device of  claim 1 , wherein the controller applies the third program voltage to the word line during the third phase in response to the resumption command. 
     
     
         7 . The device of  claim 1 , wherein the controller performs operations based on commands from an external memory controller. 
     
     
         8 . A nonvolatile semiconductor memory device comprising:
 a word line connected to a memory cell array; and   a controller configured to be capable of applying a voltage to the word line, perform a write operation upon reception of a write command, and output a busy signal representing that the write operation is progressing,   wherein the write operation includes a first phase and a second phase that are executed in the order given,   the controller performs applies a first program voltage to the word line during the first phase; interrupts the write operation if an interruption command is received during the first phase; resumes the write operation if a resumption command is received after the interruption; applies a second program voltage to the word line during the second phase after the resumption; and the second program voltage is higher than the first program voltage.   
     
     
         9 . The device of  claim 8 , wherein the controller outputs a ready signal after the interruption, and outputs a busy signal after resumption of the write signal. 
     
     
         10 . The device of  claim 9 , wherein the controller performs a read operation if a read command is received after the interruption, and is capable of receiving the resumption command after completion of the read operation. 
     
     
         11 . The device of  claim 10 , wherein the controller outputs a busy signal during the read operation. 
     
     
         12 . The device of  claim 8 , wherein the controller performs a first verify operation before applying the second program voltage to the word line during the second phase if the resumption command is received. 
     
     
         13 . The device of  claim 8 , wherein the controller applies the second program voltage to the word line during the second phase in response to the resumption command. 
     
     
         14 . The device of  claim 8 , wherein the controller performs operations based on commands from an external memory controller.