Methods for Cell Boundary Encroachment and Semiconductor Devices Implementing the Same

Abstract

A semiconductor device is disclosed to include a plurality of cells. Each of the cells has a respective outer cell boundary defined to circumscribe the cell in an orthogonal manner. Also, each of the cells includes circuitry for performing one or more logic functions. This circuitry includes a plurality of conductive features defined in one or more levels of the cell. One or more of the conductive features in at least one level of a given cell is an encroaching feature positioned to encroach by an encroachment distance into an exclusion zone. The exclusion zone occupies an area within the cell defined by an exclusion distance extending perpendicularly inward into the given cell from a first segment of the outer cell boundary. The exclusion distance is based on a design rule distance representing a minimum separation distance required between conductive features in adjacently placed cells on the semiconductor device.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a first cell including circuitry for performing one or more logic functions, the first cell including a first plurality of conductive structures formed in a given level of the semiconductor device, the first plurality of conductive structures including a two-dimensionally varying conductive structure that includes a first segment oriented to extend lengthwise in a first direction across the first cell and a second segment oriented to extend lengthwise in a second direction across the first cell, the second direction perpendicular to the first direction, and both the first direction and the second direction parallel to a substrate of the semiconductor device, the second segment formed contiguous with the first segment, the second segment located within an exclusion zone along a side boundary of the first cell; and   a second cell including circuitry for performing one or more logic functions, the second cell placed side-by-side with the first cell with a side boundary of the second cell aligned with the side boundary of the first cell, the second cell including a second plurality of conductive structures formed in the given level of the semiconductor device, the second cell including a spacing allowance region located along the side boundary of the second cell, the spacing allowance region sized to provide at least a design rule spacing between the second segment of the two-dimensionally varying conductive structure in the first cell and any of the second plurality of conductive structures in the second cell.   
     
     
         2 . The semiconductor device as recited in  claim 1 , wherein the two-dimensionally varying conductive structure of the first cell includes a third segment oriented to extend lengthwise in the first direction across the first cell, the third segment formed contiguous with the second segment. 
     
     
         3 . The semiconductor device as recited in  claim 2 , wherein the first segment of the two-dimensionally varying conductive structure of the first cell has a lengthwise centerline oriented in the first direction, and wherein the third segment of the two-dimensionally varying conductive structure of the first cell has a lengthwise centerline oriented in the first direction, wherein the first segment and the third segment of the two-dimensionally varying conductive structure of the first cell have their lengthwise centerlines positioned on respective virtual lines of a virtual grate, wherein the virtual grate is defined as a set of parallel virtual lines extending in the first direction across the given level of the semiconductor device, wherein adjacent virtual lines of the virtual grate are separated from each other by a virtual grate pitch as measured in the second direction. 
     
     
         4 . The semiconductor device as recited in  claim 3 , wherein the first segment and the third segment of the two-dimensionally varying conductive structure of the first cell have their lengthwise centerlines separated by three times the virtual grate pitch as measured in the second direction. 
     
     
         5 . The semiconductor device as recited in  claim 4 , wherein the first plurality of conductive structures of the first cell includes a first linear-shaped conductive structure and a second linear-shaped conductive structure, the first linear-shaped conductive structure and the second linear-shaped conductive structure positioned between the first segment and the third segment of the two-dimensionally varying conductive structure of the first cell. 
     
     
         6 . The semiconductor device as recited in  claim 5 , wherein the first linear-shaped conductive structure has a lengthwise centerline oriented in the first direction, wherein the second linear-shaped conductive structure has a lengthwise centerline oriented in the first direction, wherein the first and second linear-shaped conductive structures have their lengthwise centerlines positioned on respective virtual lines of the virtual grate. 
     
     
         7 . The semiconductor device as recited in  claim 6 , wherein a first end of the first linear-shaped conductive structure is substantially aligned in the first direction with a first end of the second linear-shaped conductive structure. 
     
     
         8 . The semiconductor device as recited in  claim 7 , wherein the first end of the first linear-shaped conductive structure and the first end of the second linear-shaped conductive structure are positioned next to and spaced apart from the second segment of the two-dimensionally varying conductive structure of the first cell. 
     
     
         9 . The semiconductor device as recited in  claim 8 , wherein a second end of the first linear-shaped conductive structure is substantially aligned in the first direction with a second end of the second linear-shaped conductive structure. 
     
     
         10 . The semiconductor device as recited in  claim 9 , wherein an end of the first segment of the two-dimensionally varying conductive structure of the first cell is substantially aligned in the first direction with both the second end of the first linear-shaped conductive structure and the second end of the second linear-shaped conductive structure. 
     
     
         11 . The semiconductor device as recited in  claim 10 , wherein an end of the third segment of the two-dimensionally varying conductive structure of the first cell is substantially aligned in the first direction with both the second end of the first linear-shaped conductive structure and the second end of the second linear-shaped conductive structure. 
     
     
         12 . The semiconductor device as recited in  claim 11 , wherein the side boundary of the first cell along which the exclusion zone is located is a first side boundary of the first cell, wherein the first cell includes a second side boundary located opposite the first cell from the first side boundary of the first cell, wherein the first cell includes a spacing allowance region located between the second side boundary of the first cell and each of the end of the first segment of the two-dimensionally varying conductive structure and the second end of the first linear-shaped conductive structure and the second end of the second linear-shaped conductive structure and the end of the third segment of the two-dimensionally varying conductive structure. 
     
     
         13 . The semiconductor device as recited in  claim 12 , wherein a size of the spacing allowance region of the first cell as measured in the first direction is substantially equal to a size of the spacing allowance region of the second cell as measured in the first direction. 
     
     
         14 . The semiconductor device as recited in  claim 13 , wherein the first plurality of conductive structures of the first cell includes a third linear-shaped conductive structure having a lengthwise centerline oriented in the first direction, the third linear-shaped conductive structure having its lengthwise centerline positioned one virtual grate pitch as measured in the second direction away from the lengthwise centerline of the first segment of the two-dimensionally varying conductive structure of the first cell. 
     
     
         15 . The semiconductor device as recited in  claim 14 , wherein the exclusion zone along the first side boundary of the first cell is a first exclusion zone, wherein the third linear-shaped conductive structure has a first end located within a second exclusion zone along the second side boundary of the first cell. 
     
     
         16 . The semiconductor device as recited in  claim 15 , wherein said spacing allowance region of the first cell is a first spacing allowance region of the first cell, wherein the first cell includes a second spacing allowance region located between a second end of the third linear-shaped conductive structure and the first side boundary of the first cell, wherein the second spacing allowance region is sized to provide at least a design rule spacing between the second end of the third linear-shaped conductive structure and any of the second plurality of conductive structures in the second cell. 
     
     
         17 . The semiconductor device as recited in  claim 16 , wherein the first plurality of conductive structures of the first cell includes a fourth linear-shaped conductive structure having a lengthwise centerline oriented in the first direction, the fourth linear-shaped conductive structure having its lengthwise centerline positioned one virtual grate pitch as measured in the second direction away from the lengthwise centerline of the third segment of the two-dimensionally varying conductive structure. 
     
     
         18 . The semiconductor device as recited in  claim 17 , wherein the fourth linear-shaped conductive structure has a first end located within the second exclusion zone along the second side boundary of the first cell. 
     
     
         19 . The semiconductor device as recited in  claim 18 , wherein the first cell includes a third spacing allowance region located between a second end of the fourth linear-shaped conductive structure and the first side boundary of the first cell, wherein the third spacing allowance region is sized to provide at least a design rule spacing between the second end of the fourth linear-shaped conductive structure and any of the second plurality of conductive structures in the second cell. 
     
     
         20 . A method for fabricating a semiconductor device, comprising:
 forming a first cell including circuitry for performing one or more logic functions, wherein forming the first cell includes forming a first plurality of conductive structures in a given level of the semiconductor device, the first plurality of conductive structures including a two-dimensionally varying conductive structure that includes a first segment oriented to extend lengthwise in a first direction across the first cell and a second segment oriented to extend lengthwise in a second direction across the first cell, the second direction perpendicular to the first direction, and both the first direction and the second direction parallel to a substrate of the semiconductor device, the second segment formed contiguous with the first segment, the second segment located within an exclusion zone along a side boundary of the first cell; and   forming a second cell including circuitry for performing one or more logic functions, the second cell placed side-by-side with the first cell with a side boundary of the second cell aligned with the side boundary of the first cell, wherein forming the second cell includes forming a second plurality of conductive structures in the given level of the semiconductor device, the second cell including a spacing allowance region located along the side boundary of the second cell, the spacing allowance region sized to provide at least a design rule spacing between the second segment of the two-dimensionally varying conductive structure in the first cell and any of the second plurality of conductive structures in the second cell.