Semiconductor structure and method of forming the same

Abstract

Provided is a semiconductor structure including a substrate, a first gate, a second gate, a third gate and an inter-gate dielectric layer. The substrate has a first area and a second area, and the first surface of the first area is lower than the second surface of the second area. The first gate is disposed on the first surface of the first area. The second gate includes metal and is disposed on the first gate. The inter-gate dielectric layer is disposed between the first and second gates. The third gate includes metal and is disposed on the second surface of the second area. A method of foaming a semiconductor structure is further provided.

1 . A semiconductor structure, comprising:
 a substrate, having a first area and a second area, wherein a first surface of the first area is lower than a second surface of the second area;   a first gate, disposed on the first surface of the first area;   a second gate, disposed on the first gate and comprising metal;   an inter-gate dielectric layer, disposed between the second gate and the first gate; and   a third gate, disposed on the second surface of the second area and comprising metal,   wherein the first gate and the second gate comprise different materials.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein a surface of the inter-gate dielectric layer is substantially coplanar with the second surface. 
     
     
         3 . The semiconductor structure of  claim 1 , further comprising a fourth gate disposed on the first surface at one side of the first gate. 
     
     
         4 . The semiconductor structure of  claim 3 , wherein each of the first gate and the fourth gate comprises a silicon-containing material. 
     
     
         5 . The semiconductor structure of  claim 3 , further comprising:
 a plurality of first doped regions, disposed in the substrate beside the first gate and beside the fourth gate, wherein the first gate and the fourth gate share one of the first doped regions; and   a plurality of second doped regions, disposed in the substrate beside the third gate.   
     
     
         6 . The semiconductor structure of  claim 1 , wherein the inter-gate dielectric layer comprises an ONO dielectric layer, a high-dielectric-constant (high-k) layer having a dielectric constant of greater than about 10 or a combination thereof. 
     
     
         7 . The semiconductor structure of  claim 1 , wherein the first area is a cell area, and the second area is a periphery area. 
     
     
         8 . The semiconductor structure of  claim 1 , further comprising:
 a first insulating layer, disposed between the first gate and the substrate; and   a second insulating layer, disposed between the third gate and the substrate.   
     
     
         9 . The semiconductor structure of  claim 8 , further comprising a high-k layer having a dielectric constant of greater than about 10 disposed between the third gate and the second insulating layer. 
     
     
         10 . The semiconductor structure of  claim 1 , wherein the first gate is a floating gate, the second gate is a control gate, and the third gate is a logic gate. 
     
     
         11 . A method of forming a semiconductor structure, comprising:
 providing a substrate having a first area and a second area, wherein a first surface of the first area is lower than a second surface of the second area;   sequentially forming a first insulating layer, a first gate, a first dielectric layer and a first dummy gate on the first surface of the first area;   forming a second dielectric layer and a second dummy gate on the second surface of the second area;   forming an inter-layer dielectric layer around the first gate, the first dummy gate and the second dummy gate;   removing the first dummy gate and the second dummy gate, so as to form a first trench and a second trench in the inter-layer dielectric layer; and   filling a second gate and a third gate respectively in the first trench and the second trench,   wherein the first gate and the second gate comprise different materials.   
     
     
         12 . The method of  claim 11 , wherein each of the second gate and the third gate comprises metal. 
     
     
         13 . The method of  claim 11 , wherein a surface of the first dielectric layer is substantially coplanar with the second surface. 
     
     
         14 . The method of  claim 11 , further comprising forming a fourth gate on the first surface at one side of the first gate, wherein the fourth gate and the first gate are formed simultaneously. 
     
     
         15 . The method of  claim 14 , wherein a method of forming the first gate, the first dummy gate, the second dummy gate and the fourth gate comprises:
 sequentially forming a first insulating material layer and a first conductive layer on the substrate in the first area;   forming a first dielectric material layer on the first conductive layer in the first area and forming a second dielectric material layer on the substrate in the second area;   forming a second conductive layer on the first dielectric material layer and on the second dielectric material layer;   performing a first patterning step, so as to form a first stacked structure and a second stacked structure on the substrate in the first area, wherein the first stacked structure comprises the first insulating layer, the first gate, the first dielectric layer and the first dummy gate; and   performing a second patterning step, so as to form the second dielectric layer and the second dummy gate on the substrate in the second area, wherein during the second patterning step, a portion of the second stacked structure is simultaneously removed and the fourth gate remains.   
     
     
         16 . The method of  claim 15 , wherein each of the first conductive layer and the second conductive layer comprises a silicon-containing material. 
     
     
         17 . The method of  claim 14 , further comprising:
 forming a plurality of first doped regions in the substrate beside the first gate and beside the fourth gate, wherein the first gate and the fourth gate share one of the first doped regions; and   forming a plurality of second doped regions in the substrate beside the third gate.   
     
     
         18 . The method of  claim 11 , wherein the first dielectric layer comprises an ONO dielectric layer, a high-k layer having a dielectric constant of greater than about 10 or a combination thereof. 
     
     
         19 . The method of  claim 11 , wherein the first area is a cell area, the second area is a periphery area. 
     
     
         20 . The method of  claim 11 , wherein the first gate is a floating gate, the second gate is a control gate, and the third gate is a logic gate.