US2017098629A1PendingUtilityA1

Stacked fan-out package structure

48
Assignee: MEDIATEK INCPriority: Oct 5, 2015Filed: Jul 25, 2016Published: Apr 6, 2017
Est. expiryOct 5, 2035(~9.2 yrs left)· nominal 20-yr term from priority
Inventors:Nai-Wei LiuTzu-Hung LinI-Hsuan PengChing-Wen HsiaoWei-Che Huang
H10W 90/734H10W 90/732H10W 74/121H10W 74/019H10W 72/9413H10W 72/07307H10W 72/874H10W 72/241H10W 72/0198H10W 72/073H10W 70/655H10W 70/099H10W 70/09H10W 90/701H10W 70/614H10W 70/60H10W 90/00H10W 74/129H10W 74/131H01L 25/0657H01L 2225/06572H01L 2225/06548H01L 25/50H01L 2225/06586H01L 23/564H01L 2225/06555
48
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Claims

Abstract

A semiconductor package structure is provided. The structure includes a first semiconductor die having a first surface and a second surface opposite thereto. A first molding compound surrounds the first semiconductor die. A first redistribution layer (RDL) structure is disposed on the second surface of the first semiconductor die and laterally extends on the first molding compound. A second semiconductor die is disposed on the first RDL structure and has a first surface and a second surface opposite thereto. A second molding compound surrounds the second semiconductor die. A first protective layer covers a sidewall of the first RDL structure and a sidewall of the first molding compound.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A semiconductor package structure, comprising:
 a first semiconductor die having a first surface and a second surface opposite thereto;   a first molding compound surrounding the first semiconductor die;   a first redistribution layer (RDL) structure disposed on the second surface of the first semiconductor die and laterally extending on the first molding compound;   a second semiconductor die disposed on the first RDL structure and having a first surface and a second surface opposite thereto;   a second molding compound surrounding the second semiconductor die; and   a first protective layer covering a sidewall of the first RDL structure and a sidewall of the first molding compound.   
     
     
         2 . The semiconductor package structure as claimed in  claim 1 , wherein the first protective layer is an extending portion of the second molding compound. 
     
     
         3 . The semiconductor package structure as claimed in  claim 1 , further comprising a second RDL structure that is disposed on the second surface of the second semiconductor die and laterally extends on the second molding compound. 
     
     
         4 . The semiconductor package structure as claimed in  claim 3 , wherein a sidewall of the second RDL structure is not vertically aligned with the sidewall of the first RDL structure. 
     
     
         5 . The semiconductor package structure as claimed in  claim 3 , further comprising:
 a plurality of bumps disposed on and electrically coupled to the second RDL structure; and   a plurality of through vias passing through the second molding compound and electrically coupled between the first RDL structure and the second RDL structure.   
     
     
         6 . The semiconductor package structure as claimed in  claim 3 , further comprising:
 a third semiconductor die disposed on the second RDL structure and having a first surface and a second surface opposite thereto; and   a third molding compound surrounding the third semiconductor die.   
     
     
         7 . The semiconductor package structure as claimed in  claim 6 , wherein the first protective layer covering a sidewall of the second RDL structure and a sidewall of the second molding compound. 
     
     
         8 . The semiconductor package structure as claimed in  claim 7 , wherein the first protective layer is an extending portion of the third molding compound. 
     
     
         9 . The semiconductor package structure as claimed in  claim 6 , further comprising a second protective layer covering a sidewall of the second RDL structure, a sidewall of the second molding compound, and a sidewall of the first protective layer. 
     
     
         10 . The semiconductor package structure as claimed in  claim 9 , wherein the first protective layer is an extending portion of the second molding compound and the second protective layer is an extending portion of the third molding compound. 
     
     
         11 . The semiconductor package structure as claimed in  claim 9 , further comprising a third RDL structure disposed on the second surface of the third semiconductor die and laterally extending on the third molding compound. 
     
     
         12 . The semiconductor package structure as claimed in  claim 11 , wherein a sidewall of the third RDL structure is not vertically aligned with the sidewall of the first RDL structure or the sidewall of the second RDL structure. 
     
     
         13 . The semiconductor package structure as claimed in  claim 12 , further comprising:
 a plurality of bumps disposed on and electrically coupled to the third RDL structure; and   a plurality of through vias passing through the third molding compound and electrically coupled between the second RDL structure and the third RDL structure.   
     
     
         14 . The semiconductor package structure as claimed in  claim 6 , further comprising a second protective layer covering a sidewall of the second RDL structure and disposed on the second molding compound. 
     
     
         15 . The semiconductor package structure as claimed in  claim 14 , wherein the first protective layer is an extending portion of the second molding compound and the second protective layer is an extending portion of the third molding compound. 
     
     
         16 . The semiconductor package structure as claimed in  claim 14 , further comprising a third RDL structure disposed on the second surface of the third semiconductor die and laterally extending on the third molding compound. 
     
     
         17 . The semiconductor package structure as claimed in  claim 16 , wherein a sidewall of the third RDL structure is not vertically aligned with the sidewall of the first RDL structure or the sidewall of the second RDL structure. 
     
     
         18 . The semiconductor package structure as claimed in  claim 16 , further comprising:
 a plurality of bumps disposed on and electrically coupled to the third RDL structure; and   a plurality of through vias passing through the third molding compound and electrically coupled between the second RDL structure and the third RDL structure.   
     
     
         19 . The semiconductor package structure as claimed in  claim 1 , further comprising a backside film disposed on the first surface of the first semiconductor die. 
     
     
         20 . A semiconductor package structure, comprising:
 a first semiconductor die having a first surface and a second surface opposite thereto;   a first RDL structure disposed on the second surface of the first semiconductor die;   a second semiconductor die disposed on the first RDL structure and having a first surface and a second surface opposite thereto, wherein the second semiconductor die has smaller dimensions than the first semiconductor die, so that a portion of the first RDL structure is exposed from the second semiconductor die; and   a second molding compound disposed on the exposed portion of the first RDL structure and surrounding the second semiconductor die, wherein the second molding compound has an extending portion covering a sidewall of the first RDL structure.   
     
     
         21 . The semiconductor package structure as claimed in  claim 20 , wherein the extending portion of the second molding compound partially covers a sidewall of the first semiconductor die. 
     
     
         22 . The semiconductor package structure as claimed in  claim 20 , wherein the extending portion of the second molding compound entirely covers a sidewall of the first semiconductor die. 
     
     
         23 . The semiconductor package structure as claimed in  claim 20 , further comprising a second RDL structure disposed on the second surface of the second semiconductor die and laterally extending on the second molding compound. 
     
     
         24 . The semiconductor package structure as claimed in  claim 23 , wherein a sidewall of the second RDL structure is not vertically aligned with the sidewall of the first RDL structure. 
     
     
         25 . The semiconductor package structure as claimed in  claim 23 , further comprising:
 a plurality of bumps disposed on and electrically coupled to the second RDL structure; and   a plurality of through vias passing through the second molding compound and electrically coupled between the first RDL structure and the second RDL structure.   
     
     
         26 . The semiconductor package structure as claimed in  claim 20 , further comprising a backside film disposed on the first surface of the first semiconductor die.

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