Semiconductor device having trench gate structure and method for manufacturing the semiconductor device

Abstract

A semiconductor device of the present invention includes a semiconductor layer in which a gate trench is formed, a gate insulating film formed along an inner surface of the gate trench, a gate electrode that is buried in the gate trench through the gate insulating film and that has a lower electrode and an upper electrode that are separated upwardly and downwardly from each other with an intermediate insulating film between the lower electrode and the upper electrode, and a gate contact that is formed in the gate trench so as to pass through the upper electrode and through the intermediate insulating film and so as to reach the lower electrode and that electrically connects the lower electrode and the upper electrode together.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a semiconductor layer in which a gate trench is formed;   a gate insulating film formed along an inner surface of the gate trench;   a gate electrode that is buried in the gate trench through the gate insulating film and that has a lower electrode and an upper electrode that are separated upwardly and downwardly from each other with an intermediate insulating film between the lower electrode and the upper electrode; and   an opening connecting the lower electrode and the upper electrode together.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein the lower electrode includes a convex portion protruding toward the opening side of the gate trench, and
 the convex portion is electrically connected with the upper electrode.   
     
     
         3 . The semiconductor device according to  claim 1 , wherein the upper electrode includes a central portion and a peripheral portion surrounding the central portion at a bottom of the upper electrode, and
 the central portion is positioned at a shallower level than the peripheral portion.   
     
     
         4 . The semiconductor device according to  claim 1 , wherein the upper electrode has a width wider than that of the lower electrode. 
     
     
         5 . The semiconductor device according to according to  claim 1 , further comprising a gate contact is formed in the opening and is in contact with the lower electrode and the upper electrode. 
     
     
         6 . The semiconductor device according to  claim 1 , further comprising:
 a second conductivity type body region formed at a surface portion of the semiconductor layer; and   a first conductivity type region formed in the body region,   wherein the gate insulating film includes:
 a thick film portion contiguous to the lower electrode; and 
 a thin film portion that is smaller in thickness than the thick film portion and that is interposed between the upper electrode and the body region. 
   
     
     
         7 . The semiconductor device according to  claim 6 , wherein the thin film portion of the gate insulating film has a thickness of 1/10 or less with respect to the thick film portion of the gate insulating film. 
     
     
         8 . The semiconductor device according to  claim 6 , further comprising a contact for use in the first conductivity type region, the contact being formed so as to pass through the first conductivity type region and so as to reach the body region. 
     
     
         9 . The semiconductor device according to  claim 8 , wherein the contact for use in the first conductivity type region is formed along the longitudinal direction of the gate trench. 
     
     
         10 . The semiconductor device according to  claim 8 , wherein the contact for use in the first conductivity type region includes tungsten. 
     
     
         11 . The semiconductor device according to  claim 1 , wherein the semiconductor layer includes an element region electrically separated by a DTI (Deep Trench Isolation) structure,
 the DTI structure comprising:   a DTI insulating film formed along an inner surface of a DTI trench formed in the semiconductor layer;   a DTI electrode that is buried in the DTI trench through the DTI insulating film and that has a lower DTI electrode and an upper DTI electrode that are separated upwardly and downwardly from each other with the DTI intermediate insulating film between the lower DTI electrode and the upper DTI electrode; and   a DTI contact that is formed in the DTI trench so as to pass through the upper DTI electrode and through the DTI intermediate insulating film and so as to reach the lower DTI electrode and that electrically connects the lower DTI electrode and the upper DTI electrode together.   
     
     
         12 . The semiconductor device according to  claim 11 , wherein a ground potential is applied to the DTI contact. 
     
     
         13 . The semiconductor device according to  claim 11 , wherein the element region includes a CMIS (Complementary MIS) region, the CMIS region having a first conductivity type MISFET (Metal-Insulator-Semiconductor Field-Effect Transistor) and a second conductivity type MISFET. 
     
     
         14 . A method for manufacturing a semiconductor device, the method comprising:
 a step of forming a gate trench in a semiconductor layer;   a step of forming a gate insulating film along an inner surface of the gate trench;   a step of forming a lower electrode by burying a conductive material to a halfway portion in a depth direction of the gate trench;   a step of forming an intermediate insulating film by coating the lower electrode with an insulating film;   a step of forming an upper electrode by burying a conductive material so as to backfill the gate trench from above the intermediate insulating film; and   a step of forming an opening so as to connect the lower electrode and the upper electrode together by allowing the opening to pass through the upper electrode and through the intermediate insulating film and to reach the lower electrode.   
     
     
         15 . The method for manufacturing the semiconductor device according to  claim 14 , further comprising a step of forming a gate contact in the opening so as to contact the lower electrode and the upper electrode. 
     
     
         16 . The method for manufacturing the semiconductor device according to  claim 14 , the method further comprising:
 a step of, prior to a step of forming the intermediate insulating film, allowing the gate insulating film contiguous to the lower electrode to remain as a thick film portion by selectively removing the gate insulating film to the halfway portion in the depth direction of the gate trench;   the step of forming the intermediate insulating film including a step of forming the insulating film that has a thickness smaller than the thick film portion along the inner surface of the gate trench from which the gate insulating film has been removed and forming a thin film portion serving as the gate insulating film;   a step of forming a body region facing the upper electrode with the thin film portion of the gate insulating film between the body region and the upper electrode by implanting a second conductivity type impurity into a surface portion of the semiconductor layer; and   a step of forming a first conductivity type region by implanting a first conductivity type impurity into a surface portion of the semiconductor layer in the body region.   
     
     
         17 . The method for manufacturing the semiconductor device according to  claim 16 , the method further comprising a step of forming a contact for the first conductivity type region, the contact passing through the first conductivity type region and reaching the body region. 
     
     
         18 . The method for manufacturing the semiconductor device according to  claim 17 , wherein the contact for the first conductivity type region is formed, the contact including tungsten.