Water and Ion Barrier for III-V Semiconductor Devices

Abstract

A semiconductor device includes an III-V semiconductor body, a device formed in the III-V semiconductor body, one or more metal layers above the III-V semiconductor body, an interlayer dielectric adjacent each metal layer, a plurality of vias electrically connecting each metal layer to the device formed in the III-V semiconductor body, and a barrier disposed below the uppermost metal layer and in or above the lowermost interlayer dielectric. The barrier is configured to prevent water, water ions, sodium ions and potassium ions from diffusing into the interlayer dielectric or portion of the interlayer dielectric immediately below the barrier. Methods of manufacturing the semiconductor device are also provided.

1 . A semiconductor device, comprising:
 an III-V semiconductor body;   a device formed in the III-V semiconductor body;   one or more metal layers above the III-V semiconductor body;   an interlayer dielectric adjacent each metal layer;   a plurality of vias electrically connecting each metal layer to the device formed in the III-V semiconductor body; and   a barrier disposed below the uppermost metal layer and in or above the lowermost interlayer dielectric, the barrier configured to prevent water, water ions, sodium ions and potassium ions from diffusing into the interlayer dielectric or portion of the interlayer dielectric immediately below the barrier.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the barrier comprises silicon oxynitride or silicon nitride. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the barrier is interposed between a first oxide layer and a second oxide layer of the same interlayer dielectric or between two adjacent interlayer dielectrics. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the barrier is touching and being supported by a top surface of one interlayer dielectric. 
     
     
         5 . The semiconductor device of  claim 1 , wherein the barrier is touching and being supported by a top surface of the uppermost interlayer dielectric, and wherein the barrier extends under metal lines of the uppermost metal layer. 
     
     
         6 . The semiconductor device of  claim 1 , further comprising:
 a passivation layer touching and being supported by a top surface of the uppermost metal layer; and   an electrically conductive liner interposed between each metal line of the uppermost metal layer and the interlayer dielectric immediately below the uppermost metal layer, each electrically conductive liner extending outward beyond opposing side faces of the metal line above that electrically conductive liner.   
     
     
         7 . The semiconductor device of  claim 1 , wherein the barrier comprises a plurality of layers of different materials interposed between a first oxide layer and a second oxide layer of the same interlayer dielectric or between two adjacent interlayer dielectrics. 
     
     
         8 . The semiconductor device of  claim 1 , further comprising:
 an additional barrier disposed below the uppermost metal layer and in or on a different interlayer dielectric than the other barrier, the additional barrier configured to prevent water, water ions, sodium ions and potassium ions from diffusing into the interlayer dielectric or portion of the interlayer dielectric immediately below the additional barrier.   
     
     
         9 . The semiconductor device of  claim 8 , wherein the barriers comprise different materials. 
     
     
         10 . The semiconductor device of  claim 8 , further comprising:
 an electrically conductive liner interposed between each metal line of the metal layer immediately above the additional barrier and the interlayer dielectric immediately below that metal layer, each electrically conductive liner extending outward beyond opposing side faces of the metal line above that electrically conductive liner.   
     
     
         11 . The semiconductor device of  claim 1 , further comprising:
 a passivation layer touching and being supported by a top surface of the III-V semiconductor body,   wherein the lowermost interlayer dielectric is touching and being supported by a top surface of the passivation layer,   wherein the passivation layer does not prevent diffusion of water, water ions, sodium ions and potassium ions into the III-V semiconductor body.   
     
     
         12 . The semiconductor device of  claim 1 , wherein an uppermost layer of the III-V semiconductor body comprises an III-nitride material. 
     
     
         13 . A method of manufacturing a semiconductor device, the method comprising:
 forming a device in an III-V semiconductor body;   forming one or more metal layers above the III-V semiconductor body;   forming an interlayer dielectric adjacent each metal layer;   forming a plurality of vias electrically connecting each metal layer to the device formed in the III-V semiconductor body; and   forming a harrier below the uppermost metal layer and in or above the lowermost interlayer dielectric, the barrier configured to prevent water, water ions, sodium ions and potassium ions from diffusing into the interlayer dielectric or portion of the interlayer dielectric immediately below the barrier.   
     
     
         14 . The method of  claim 13 , wherein forming the harrier comprises:
 depositing a first oxide layer of one of the interlayer dielectrics;   depositing silicon oxynitride or silicon nitride on the first oxide layer; and   depositing a second oxide layer of the interlayer dielectric on the silicon oxynitride.   
     
     
         15 . The method of  claim 13 , wherein forming the barrier comprises:
 depositing silicon nitride or silicon oxynitride on one interlayer dielectric.   
     
     
         16 . The method of  claim 13 , wherein forming the barrier comprises:
 depositing the barrier on the uppermost interlayer dielectric so that the barrier extends under metal lines of the uppermost metal layer.   
     
     
         17 . The method of  claim 13 , further comprising:
 forming a passivation layer on the uppermost metal layer; and   forming an electrically conductive liner between each metal line of the uppermost metal layer and the interlayer dielectric immediately below the uppermost metal layer, each electrically conductive liner extending outward beyond opposing side faces of the metal line above that electrically conductive liner.   
     
     
         18 . The method of  claim 13 , further comprising:
 forming an additional barrier below the uppermost metal layer and in or on a different interlayer dielectric than the other barrier, the additional barrier configured to prevent water, water ions, sodium ions and potassium ions from diffusing into the interlayer dielectric or portion of the interlayer dielectric immediately below the additional barrier.   
     
     
         19 . The method of  claim 18 , further comprising:
 forming an electrically conductive liner between each metal line of the metal layer immediately above the additional barrier and the interlayer dielectric immediately below that metal layer, each electrically conductive liner extending outward beyond opposing side faces of the metal line above that electrically conductive liner.   
     
     
         20 . The method of  claim 13 , wherein forming the barrier comprises:
 depositing by chemical vapor deposition a silane-ammonia mixture on one of the interlayer dielectrics or on an oxide layer of one of the interlayer dielectrics; and   controlling a flow rate of silane and ammonia during the chemical vapor deposition so that a silicon nitride layer formed by the chemical vapor deposition has a concentration of nitride sufficient to prevent water, water ions, sodium ions and potassium ions from diffusing into the interlayer dielectric or portion of the interlayer dielectric immediately below the barrier.