Semiconductor device and method for manufacturing the same

Abstract

To improve reliability of SRAM. In a memory cell of the SRAM, a coupling capacitance is provided between memory nodes in consideration of dynamic stability.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a first SRAM cell with a first capacitive element provided between a first node connected to a first bit line and a second node connected to a second bit line; and   a second SRAM cell with a second capacitive element provided between a third node connected to the first bit line and a fourth node connected to the second bit line,   wherein the first capacitive element is disposed to be closer to the first bit line side than to a middle point of the first bit line and the second bit line, and the second capacitive element is disposed to be closer to the second bit line side than to the middle point of the first bit line and the second bit line.   
     
     
         2 . The semiconductor device according to  claim 1 ,
 wherein the first capacitive element is disposed planarly overlapping the first bit line and the second capacitive element is disposed planarly overlapping the second bit line.   
     
     
         3 . The semiconductor device according to  claim 1 ,
 wherein the first bit line and the second bit line make up a single pair of bit lines in a memory cell array and the first capacitive elements and the second capacitive elements are provided in the same number between the pair of bit lines.   
     
     
         4 . The semiconductor device according to  claim 1 ,
 wherein the first SRAM cell and the second SRAM cell are disposed adjacent to each other.   
     
     
         5 . The semiconductor device according to  claim 1 ,
 wherein the first capacitive element is disposed apart from the second bit line and the second capacitive element is disposed apart from the first bit line.   
     
     
         6 . The semiconductor device according to  claim 1 ,
 wherein the first capacitive element is configured with a three-layer structure of an upper electrode, a capacitance insulation film, and a lower electrode, and the upper electrode is disposed planarly overlapping the first bit line and apart from the second bit line.   
     
     
         7 . The semiconductor device according to  claim 1 ,
 wherein the first capacitive element is configured with a three-layer structure of an upper electrode, a capacitance insulation film, and a lower electrode, and the lower electrode is disposed planarly overlapping the first bit line and apart from the second bit line.   
     
     
         8 . The semiconductor device according to  claim 3 ,
 wherein in the memory cell array, a capacitive element of another SRAM cell connected to a common word line is disposed to be closer to the same side to which the capacitive element of the first SRAM cell or the second SRAM cell connected to the word line is disposed.   
     
     
         9 . The semiconductor device according to  claim 1 ,
 wherein at least either of the first bit line and the second bit line is disposed in a layer higher than the first capacitive element and the second capacitive element.   
     
     
         10 . The semiconductor device according to  claim 1 ,
 wherein at least either of the first bit line and the second bit line is disposed in a layer lower than the first capacitive element and the second capacitive element.   
     
     
         11 . The semiconductor device according to  claim 10 ,
 wherein the first capacitive element and the second capacitive element are each configured with a three-layer structure of an upper electrode, a capacitance insulation film, and a lower electrode, and the each upper electrode is electrically connected with a transistor of the first SRAM cell and a transistor of the second SRAM cell by a plurality of contacts that are laid over a plurality of layers.   
     
     
         12 . The semiconductor device according to  claim 11 ,
 wherein the each lower electrode is electrically connected with the transistor of the first SRAM cell and the transistor of the second SRAM cell by the contacts that are laid over the layers.   
     
     
         13 . The semiconductor device according to  claim 1 ,
 wherein the semiconductor device is a DRAM-mixed-mounted semiconductor device in which a DRAM cell is mounted, and the first capacitive element and the second capacitive element are formed with the same material on the same layer as that of a capacitor of the DRAM cell.   
     
     
         14 . A method for manufacturing a semiconductor device comprising the steps of:
 (a) forming an element that constitutes an SRAM cell in an SRAM formation area of a principal plane of a semiconductor wafer and forming an element that constitutes a DRAM cell in a DRAM formation area of the principal plane of the semiconductor wafer;   (b) forming a first inter-layer insulation film that covers the element constituting the SRAM cell and the element constituting the DRAM cell on these elements;   (c) forming two pieces of wiring that electrically connect with an element constituting the SRAM cell on the first inter-layer insulation film in the SRAM formation area and serve as two memory nodes of the SRAM;   (d) forming a second inter-layer insulation film in the SRAM formation area and the DRAM formation area that covers the two pieces of wiring; and   (e) forming a three-layer lamination film of a first conductive film serving as a lower electrode of an MIM, an insulating layer serving as a capacitance insulation film of the MIM, and a second conductive film serving as an upper electrode of the MIM on the second inter-layer insulation film, and forming the MIM in each of the SRAM formation area and the DRAM formation area by dry etching,   wherein the MIM in the SRAM area is such that the lower electrode of the MIM is electrically connected with one of the two pieces of wiring and the upper electrode of the MIM is electrically connected with the other of the two pieces of wiring.   
     
     
         15 . The method for manufacturing a semiconductor device according to  claim 14 ,
 wherein the first conductive film and the second conductive film are one of a titanium nitride film, a titanium film, or a tantalum film.   
     
     
         16 . The method for manufacturing a semiconductor device according to  claim 14 ,
 wherein the insulation layer is one of a silicon nitride film, a tantalum oxide film, or a zirconium oxide film.