Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate

Abstract

A microelectronic assembly can include a circuit panel having first and second panel contacts at respective first and second surfaces thereof, and first and second microelectronic packages each having terminals mounted to the respective panel contacts. Each package can include a microelectronic element having a face and contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with an external component. The terminals can include first terminals at positions within first and second parallel grids. The first terminals can be configured to carry address information usable by circuitry within the package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element. Signal assignments of the first terminals in the first grid can be a mirror image of signal assignments of the first terminals in the second grid.

1 .- 3 . (canceled) 
     
     
         4 . A microelectronic package, comprising:
 first and second microelectronic elements each having memory storage array function, each microelectronic element having one or more columns of element contacts, each column of element contacts extending in a first direction along a face of such microelectronic element;   a substrate having first and second opposed surfaces and first and second opposed edges extending between the first and second surfaces, the first surface having first substrate contacts and second substrate contacts thereon, the first substrate contacts facing the element contacts of the first microelectronic element and joined thereto, and the second substrate contacts facing the element contacts of the second microelectronic element and joined thereto; and   a plurality of terminals exposed at the second surface of the substrate and electrically connected with the first and second substrate contacts, the terminals being disposed at positions within a plurality of columns extending along the second surface of the substrate and being configured to connect the microelectronic package to at least one component external to the microelectronic package,   the terminals including first and second duplicate sets of data terminals, the columns of the first and second duplicate sets of data terminals each extending in the first direction, wherein signal assignments of the first and second duplicate sets of data terminals are symmetric about an axis of symmetry extending in the first direction,   the terminals further including first and second duplicate sets of address terminals disposed between the first and second duplicate sets of data terminals, each of the first and second duplicate sets of address terminals being configured to carry address information.   
     
     
         5 . The microelectronic package as claimed in  claim 4 , wherein the columns of the first and second duplicate sets of address terminals each extend in the first direction. 
     
     
         6 . The microelectronic package as claimed in  claim 4 , wherein signal assignments of the first and second duplicate sets of address terminals are symmetric about the axis of symmetry. 
     
     
         7 . The microelectronic assembly as claimed in  claim 4 , the terminals further including command terminals disposed between the first and second duplicate sets of data terminals, the command terminals being configured to carry all of the command signals transferred to the microelectronic package, the command signals being write enable, row address strobe, and column address strobe signals. 
     
     
         8 . The microelectronic package as claimed in  claim 4 , further comprising a buffer chip having a surface facing the first surface of the substrate, the buffer chip being electrically connected with the address terminals, the buffer chip being configured to regenerate at least some of the address information received at the address terminals and to output the regenerated address information to the first and second microelectronic elements. 
     
     
         9 . The microelectronic package as claimed in  claim 4 , wherein the terminals further include a third set of data terminals, the columns of the third set of data terminals each extending in a second direction transverse to the first direction. 
     
     
         10 . The microelectronic package as claimed in  claim 9 , wherein signal assignments of the third set of data terminals have modulo-X symmetry about the axis of symmetry, wherein X is an integer. 
     
     
         11 . The microelectronic package as claimed in  claim 10 , wherein X is equal to 2 raised to the power of n, n being greater than or equal to 2. 
     
     
         12 . The microelectronic package as claimed in  claim 10 , wherein X is equal to N times  8 , wherein N is a whole number greater than or equal to one. 
     
     
         13 . The microelectronic package as claimed in  claim 10 , wherein X is greater than two. 
     
     
         14 . The microelectronic package as claimed in  claim 9 , wherein the terminals further include a fourth set of data terminals, the columns of the fourth set of data terminals each extending in the second direction, the third and fourth sets of data terminals being duplicate sets of the data terminals. 
     
     
         15 . The microelectronic package as claimed in  claim 14 , wherein signal assignments of the third and fourth duplicate sets of data terminals are symmetric about a second axis of symmetry extending in the second direction. 
     
     
         16 . The microelectronic package as claimed in  claim 14 , wherein the first and second duplicate sets of data terminals separate the third and fourth duplicate sets of data terminals from one another. 
     
     
         17 . The microelectronic package as claimed in  claim 4 , wherein the axis of symmetry is located within one ball pitch of the terminals of a centerline of the substrate located equidistant between the first and second opposed edges. 
     
     
         18 . The microelectronic package as claimed in  claim 4 , wherein each of the first and second microelectronic elements embody a greater number of active devices to provide memory storage array function than any other function. 
     
     
         19 . The microelectronic package as claimed in  claim 4 , wherein the memory storage array function of each of the first and second microelectronic elements is implemented in NAND flash, resistive RAM, phase-change memory, magnetic RAM, static RAM, dynamic RAM, spin-torque RAM, or content-addressable memory technology. 
     
     
         20 . The microelectronic package as claimed in  claim 4 , wherein each of the first and second microelectronic elements include a first semiconductor chip having contacts thereon joined to the substrate contacts and at least one second semiconductor chip overlying a face of the first semiconductor chip remote from the first surface of the substrate and electrically interconnected with the first semiconductor chip. 
     
     
         21 . The microelectronic package as claimed in  claim 4 , wherein the element contacts of each of the first and second microelectronic elements include redistribution contacts exposed at the front face of the respective microelectronic element, each redistribution contact being electrically connected with a contact pad of the respective microelectronic element through at least one of a trace or a via, at least some of the redistribution contacts of each of the first and second microelectronic elements being displaced from the element contacts of the respective microelectronic element in at least one direction along the front face of the respective microelectronic element. 
     
     
         22 . A system comprising a microelectronic package according to  claim 4  and one or more other electronic components electrically connected to the microelectronic package. 
     
     
         23 . The system as claimed in  claim 22 , further comprising a housing, the microelectronic package and the one or more other electronic components being assembled with the housing.