Semiconductor package

Abstract

A semiconductor package including an insulating layer, a chip, a thermal interface material, a heat-dissipating cover and a re-distribution layer is provided. The insulating layer has an accommodating opening. The chip is disposed in the accommodating opening. The chip has an active surface, a back surface opposite to the active surface and a side surface connected to the active surface and the back surface. The thermal interface material is filled in the accommodating opening for at least encapsulating the side surface of the chip and exposing the active surface. The re-distribution layer and the heat-dissipating cover are disposed on two side of the insulating layer respectively. The heat-dissipating cover is thermally coupled to the chip through the thermal interface material. The re-distribution layer directly covers the insulating layer, the active surface of the chip and the thermal interface material, and the re-distribution layer is electrically connected to the chip.

What is claimed is: 
     
         1 . A semiconductor package, comprising:
 an insulating layer, having an accommodating opening;   a chip, disposed in the accommodating opening, the chip having an active surface, a back surface opposite to the active surface and a side surface connected to the active surface and the back surface;   a thermal interface material, filled in the accommodating opening for at least encapsulating the side surface of the chip and exposing the active surface;   a heat-dissipating cover; and   a re-distribution layer, wherein the re-distribution layer and the heat-dissipating cover are disposed on two side of the insulating layer respectively, the heat-dissipating cover is thermally coupled to the chip through the thermal interface material, and the re-distribution layer directly covers the insulating layer, the active surface of the chip and the thermal interface material, and the re-distribution layer is electrically connected to the chip.   
     
     
         2 . The semiconductor package according to  claim 1 , wherein the thermal interface material covers the back surface and the side surface of the chip. 
     
     
         3 . The semiconductor package according to  claim 2 , wherein the heat-dissipating cover contacts the insulating layer and the thermal interface material. 
     
     
         4 . The semiconductor package according to  claim 1 , wherein the thermal interface material exposes the back surface of the chip, and the heat-dissipating cover contacts the insulating layer, the thermal interface material and the back surface of the chip. 
     
     
         5 . The semiconductor package according to  claim 4 , wherein the insulating layer has a first surface and a second surface opposite to the first surface, the heat-dissipating cover is disposed on the first surface, the second surface and the active surface are coplanar to each other, the re-distribution layer is disposed on the second surface and the active surface, and the back surface of the chip cuts with the first surface of the insulating layer. 
     
     
         6 . The semiconductor package according to  claim 1 , wherein the re-distribution layer comprises at least one patterned conductive layer and at least one patterned dielectric layer that are stacked alternately, and the patterned conductive layer is electrically connected to the chip. 
     
     
         7 . The semiconductor package according to  claim 1 , further comprising:
 a plurality of solder balls, electrically connected to the chip via the re-distribution layer.   
     
     
         8 . The semiconductor package according to  claim 7 , wherein the solder balls and the chips are located on two sides of the re-distribution layer respectively. 
     
     
         9 . The semiconductor package according to  claim 1 , wherein the back surface of the chip is covered by at least one part of the heat-dissipating cover. 
     
     
         10 . The semiconductor package according to  claim 1 , wherein the side surface is perpendicular to an interface between the heat-dissipating cover and the thermal interface material. 
     
     
         11 . A semiconductor package, comprising:
 an insulating layer, having an accommodating opening;   a chip, disposed in the accommodating opening, the chip having an active surface, a back surface opposite to the active surface and a side surface connected to the active surface and the back surface;   a thermal interface material, filled in the accommodating opening for at least encapsulating the side surface of the chip and exposing the active surface, wherein the insulating layer, the thermal interface material, and the active surfaces of the chips are coplanar to each other;   a heat-dissipating cover; and   a re-distribution layer, wherein the re-distribution layer and the heat-dissipating cover are disposed on two side of the insulating layer respectively, the heat-dissipating cover is thermally coupled to the chip through the thermal interface material, and the re-distribution layer directly covers the insulating layer, the active surface of the chip and the thermal interface material, and the re-distribution layer is electrically connected to the chip.   
     
     
         12 . The semiconductor package according to  claim 11 , wherein the thermal interface material covers the back surface and the side surface of the chip. 
     
     
         13 . The semiconductor package according to  claim 12 , wherein the heat-dissipating cover contacts the insulating layer and the thermal interface material. 
     
     
         14 . The semiconductor package according to  claim 11 , wherein the thermal interface material exposes the back surface of the chip, and the heat-dissipating cover contacts the insulating layer, the thermal interface material and the back surface of the chip. 
     
     
         15 . The semiconductor package according to  claim 14 , wherein the insulating layer has a first surface and a second surface opposite to the first surface, the heat-dissipating cover is disposed on the first surface, the second surface and the active surface are coplanar to each other, the re-distribution layer is disposed on the second surface and the active surface, and the back surface of the chip cuts with the first surface of the insulating layer. 
     
     
         16 . The semiconductor package according to  claim 11 , wherein the re-distribution layer comprises at least one patterned conductive layer and at least one patterned dielectric layer that are stacked alternately, and the patterned conductive layer is electrically connected to the chip. 
     
     
         17 . The semiconductor package according to  claim 1 , further comprising:
 a plurality of solder balls, electrically connected to the chip via the re-distribution layer.   
     
     
         18 . The semiconductor package according to  claim 17 , wherein the solder balls and the chips are located on two sides of the re-distribution layer respectively. 
     
     
         19 . The semiconductor package according to  claim 11 , wherein the back surface of the chip is covered by at least one part of the heat-dissipating cover. 
     
     
         20 . The semiconductor package according to  claim 11 , wherein the side surface is perpendicular to an interface between the heat-dissipating cover and the thermal interface material.