Management of memory refresh power consumption

Abstract

Embodiments include a system, an apparatus, a device, and a method. The apparatus includes a processor, a dynamic memory, and a hardware-implemented memory control circuit. The hardware-implemented control circuit includes a control circuit for establishing an extended refresh period of the dynamic memory based at least in part on a monitored result that indicates an occurrence of a memory loss in the dynamic memory. The hardware-implemented control circuit also includes a control circuit for causing a refresh of the dynamic memory during each of at least two extended refresh periods.

1 - 36 . (canceled) 
     
     
         37 . An apparatus comprising:
 a processor;   a dynamic memory; and   a hardware-implemented memory control circuit for:
 establishing an extended refresh period of the dynamic memory based at least in part on a monitored result that indicates an occurrence of a memory loss in the dynamic memory; and 
 causing a refresh of the dynamic memory during each of at least two extended refresh periods. 
   
     
     
         38 . The apparatus of  claim 37 , further comprising:
 a semiconductor chip that includes the dynamic memory having a nominal refresh period and the hardware-implemented memory control circuit.   
     
     
         39 . The apparatus of  claim 37 , further comprising:
 a semiconductor chip that includes the dynamic memory having a nominal refresh period, the hardware-implemented memory control circuit, and the processor.   
     
     
         40 . The apparatus of  claim 37 , further comprising:
 a circuit board that operably couples the processor and the hardware-implemented memory control circuit.   
     
     
         41 . The apparatus of  claim 37 , further comprising:
 a semiconductor chip that includes the processor and the hardware-implemented memory control circuit.   
     
     
         42 . The apparatus of  claim 37 , further comprising:
 a circuit board having the processor and the hardware-implemented memory control circuit respectively operably coupled thereto; and   a communications interface operably coupled with the circuit board.   
     
     
         43 . The apparatus of  claim 37 , further comprising:
 a semiconductor chip that includes the processor and the hardware-implemented memory control circuit;   a power supply; and   a housing that encloses the power supply and the semiconductor chip.   
     
     
         44 . The apparatus of  claim 37 , further comprising:
 a communications interface; and   a circuit board having the hardware-implemented memory control circuit, the processor, the dynamic memory, and the communications interface respectively operably coupled thereto.   
     
     
         45 . The apparatus of  claim 44 , further comprising:
 a power supply.   
     
     
         46 . The apparatus of  claim 44 , further comprising:
 a housing at least substantially enclosing the circuit board having the hardware-implemented memory control circuit, the processor, the dynamic memory, and the communications interface respectively operably coupled thereto.   
     
     
         47 . The apparatus of  claim 37 , further comprising:
 a semiconductor chip that includes the processor, the dynamic memory, and the hardware-implemented memory control circuit;   a power supply;   a communications interface; and   a housing at least substantially enclosing the semiconductor chip, the power supply, and the communications interface.   
     
     
         48 . The apparatus of  claim 37 , wherein the dynamic memory includes:
 a dynamic memory implemented in at least one of a single inline memory module, a dual inline memory module, a fully buffered dual inline memory module, and/or a small outline dual inline memory module.   
     
     
         49 . The apparatus of  claim 37 , wherein the dynamic memory includes:
 a dynamic memory implemented in at least one of an information storage, a memory chip, and/or a silicon memory chip.   
     
     
         50 . The apparatus of  claim 37 , wherein the dynamic memory includes:
 a dynamic memory implemented in at least one of a quantum memory, a photonic quantum memory, and/or atomic quantum memory.   
     
     
         51 . The apparatus of  claim 37 , wherein the dynamic memory includes:
 a dynamic memory implemented in at least one of a DRAM, an EDO DRAM, a SDRAM, a RDRAM, a VRAM, and/or a DDR DRAM.   
     
     
         52 . The apparatus of  claim 37 , wherein the hardware-implemented memory control circuit for establishing an extended refresh period of the dynamic memory based at least in part on a monitored result that indicates an occurrence of a memory loss in the dynamic memory further includes:
 a hardware-implemented memory control circuit for establishing an extended refresh period of a dynamic memory having a nominal refresh period, the extended refresh period based at least in part on a monitored result that indicates an occurrence of a memory loss in the dynamic memory, and the extended refresh period being longer than the nominal refresh period.   
     
     
         53 . The apparatus of  claim 37 , wherein the hardware-implemented memory control circuit for establishing an extended refresh period of the dynamic memory based at least in part on a monitored result that indicates an occurrence of a memory loss in the dynamic memory further includes:
 a hardware-implemented memory control circuit for establishing an extended refresh period of the dynamic memory based at least in part on a monitored result that indicates an occurrence of a memory loss solvable by a periodic refresh of the dynamic memory.   
     
     
         54 - 76 . (canceled) 
     
     
         77 . A memory controller implemented in hardware, the memory controller comprising:
 an evaluation module operable to periodically determine a refresh interval of a dynamic memory, the refresh interval being responsive to a monitored result that indicates a discovered retention loss of a content of the dynamic memory; and   a manager module operable to schedule a refresh of the dynamic memory during each of at least refresh intervals.   
     
     
         78 - 81 . (canceled) 
     
     
         82 . A device comprising:
 a memory that requires a periodic refresh and having a nominal refresh period; a processor operably coupled with the memory; and   a hardware-implemented control circuit for:   periodically discovering a retention time of at least a portion of the memory that requires a periodic refresh;   determining a refresh period that is not more than the discovered retention time of the at least a portion of the memory that requires a periodic refresh; and   scheduling a refresh of the at least a portion of the memory that requires a periodic refresh at least once each refresh period.   
     
     
         83 . The device of  claim 82 , wherein the hardware-implemented control circuit for periodically discovering a retention time of at least a portion of the memory that requires a periodic refresh further includes:
 a hardware-implemented control circuit for periodically discovering a retention time of at least a portion of the memory that requires a periodic refresh, the periodically includes at least one of a period of time, an age period of the memory, a periodic measure of memory usage, and/or a response to an outcome of a memory operation.   
     
     
         84 - 93 . (canceled)