Thin film transistor panel having an etch stopper on semiconductor

Abstract

A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.

What is claimed is: 
     
         1 . A method for forming a panel comprising a thin film transistor, the method comprising:
 forming an oxide semiconductor pattern comprising a channel region;   forming an etch stopper at a position corresponding to the channel region; and   forming a first electrode and a second electrode spaced apart from the first electrode, the channel region configured to connect the first electrode to the second electrode,   wherein the etch stopper and the oxide semiconductor pattern are formed using a first mask.   
     
     
         2 . The method of  claim 1 , further comprising:
 disposing a first conductive layer on a substrate;   disposing a first insulating layer on the first conductive layer;   disposing an oxide semiconductor layer on the first insulating layer; and   disposing an etch stop layer on the oxide semiconductor layer;   wherein the etch stopper and the oxide semiconductor pattern are formed by patterning the etch stop layer and the oxide semiconductor layer using the first mask.   
     
     
         3 . The method of  claim 2 , wherein patterning the etch stop layer and the oxide semiconductor layer comprises forming a photoresist pattern using the first mask. 
     
     
         4 . The method of  claim 3 , wherein patterning the etch stop layer and the oxide semiconductor layer further comprises etching the etch stop layer having the photoresist pattern thereon to form an interim etch stopper. 
     
     
         5 . The method of  claim 4 , wherein patterning the etch stop layer and the oxide semiconductor layer further comprises etching the oxide semiconductor layer having the interim etch stopper thereon to form the oxide semiconductor pattern. 
     
     
         6 . The method of  claim 5 , wherein patterning the etch stop layer and the oxide semiconductor layer further comprises etching the interim etch stopper to form the etch stopper. 
     
     
         7 . The method of  claim 6 , wherein the interim etch stopper is formed by dry etching the etch stop layer. 
     
     
         8 . The method of  claim 7 , wherein the oxide semiconductor pattern is formed by wet etching the oxide semiconductor layer. 
     
     
         9 . The method of  claim 8 , wherein the etch stopper is formed by dry etching the interim etch stopper. 
     
     
         10 . The method of  claim 9 , wherein etching the interim etch stopper to form the etch stopper further comprises etching the first insulating layer. 
     
     
         11 . The method of  claim 6 , further comprising:
 forming a second conductive layer on the etch stopper and the oxide semiconductor pattern,   wherein the second conductive layer is patterned to form the first electrode and the second electrode.   
     
     
         12 . The method of  claim 11 , further comprising:
 forming a second insulating layer on the first electrode and the second electrode;   patterning the second insulating layer to form a contact hole exposing the first electrode; and   forming a third conductive layer on the second insulating layer;   patterning the third conductive layer to form a third electrode,   wherein the third electrode is connected to the first electrode via the contact hole.   
     
     
         13 . The method of  claim 12 , wherein the second insulating layer comprises a passivation layer. 
     
     
         14 . The method of  claim 12 , wherein the second insulating layer comprises a color filter. 
     
     
         15 . The method of  claim 12 , further comprising:
 patterning the first conductive layer to form a fourth electrode, the fourth electrode being disposed under the etch stopper and the oxide semiconductor pattern.   
     
     
         16 . The method of  claim 15 , wherein the first conductive layer is patterned using a second mask, the second conductive layer is patterned using a third mask, the second insulating layer is patterned using a fourth mask, and the third conductive layer is patterned using a fifth mask.