US2017077240A1PendingUtilityA1
Semiconductor device and method for manufacturing the same
Est. expirySep 11, 2035(~9.1 yrs left)· nominal 20-yr term from priority
H10D 64/01366H01L 29/7827H01L 21/28556H01L 29/1608H01L 29/66068H01L 29/167H01L 29/4966H01L 29/7802H01L 29/045H01L 21/049H01L 29/7395H10D 12/481H10D 64/667H10D 62/834H10D 62/405H10D 30/668H10D 30/66H10D 12/441H10D 12/031H10D 62/8325H10D 12/038H10D 64/669H10D 30/0291
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Claims
Abstract
A semiconductor device according to embodiments includes a p-type SiC region, a gate insulating film disposed on the p-type SiC region, and a gate electrode disposed on the gate insulating film and including a p-type impurity and 3 C-SiC.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A semiconductor device, comprising:
a p-type SiC region; a gate electrode including a p-type impurity and 3C-SiC; and a gate insulating film disposed between the p-type SiC region and the gate electrode.
2 . The device according to claim 1 , wherein
the gate electrode includes the p-type impurity and the 3C-SiC at least in a region contacting the gate insulating film.
3 . The device according to claim 1 , wherein
the p-type SiC region is 4H-SiC.
4 . The device according to claim 1 , wherein
the p-type impurity is aluminum (Al), gallium (Ga), or indium (In).
5 . The device according to claim 1 , wherein
a concentration of the p-type impurity in the gate electrode is equal to or more than 1×10 19 cm −3 .
6 . The device according to claim 1 , wherein
a concentration of a p-type impurity in the p-type SiC region is equal to or less than 1×10 10 cm −3 .
7 . The device according to claim 1 , wherein
the volume of the 3C-SiC in the gate electrode is larger than the volume of 4H-SiC in the gate electrode.
8 . The device according to claim 1 , wherein
the gate insulating film is a silicon oxide film.
9 . A method for manufacturing a semiconductor device, comprising:
forming a gate insulating film on a p-type SiC region; and forming, on the gate insulating film, a gate electrode including a p-type impurity and 3C-SiC at a temperature of equal to or less than 1,200° C.
10 . The method according to claim 9 , wherein
the forming of the gate electrode includes depositing a 3C-SiC layer including the p-type impurity by chemical vapor deposition (CVD) at a temperature of equal to or less than 1,200° C.
11 . The method according to claim 9 , wherein
the forming of the gate electrode includes depositing a silicon film including the p-type impurity and performing heat treatment to carbonize the silicon film at a temperature of equal to or less than 1,200° C.
12 . The method according to claim 11 , wherein
the heat treatment is performed in an atmosphere including ethane (C 2 H 6 ), ethylene (C 2 H 6 ), or acetylene (C 2 H 2 ).
13 . The method according to claim 9 , wherein
the p-type impurity is aluminum (Al), gallium (Ga), or indium (In).Join the waitlist — get patent alerts
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