US2017069751A1PendingUtilityA1

Vertical power mosfet

Assignee: RENESAS ELECTRONICS CORPPriority: Oct 24, 2012Filed: Nov 18, 2016Published: Mar 9, 2017
Est. expiryOct 24, 2032(~6.3 yrs left)· nominal 20-yr term from priority
Inventors:Tomohiro Tamaki
H10P 30/2042H10P 30/21H01L 29/0869H01L 29/7813H01L 29/41741H01L 29/66068H01L 29/0696H01L 29/1095H01L 29/0865H01L 29/0882H01L 29/66712H01L 29/7811H01L 29/1608H01L 29/0634H01L 21/046H10D 64/519H10D 30/0297H10D 64/252H10D 62/8325H10D 62/393H10D 62/158H10D 62/157H10D 62/155H10D 62/154H10D 62/127H10D 62/111H10D 30/668H10D 30/0295H10D 30/0291H10D 30/66H10D 12/031H10D 30/665H10P 30/28
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Claims

Abstract

Vertical power MOSFETs having a super junction are devices capable of having a lower on resistance than other vertical power MOSFETs. Although they have the advantage of high-speed switching due to rapid depletion of an N type drift region at the time of turn off in switching operation, they are likely to cause ringing. A vertical power MOSFET having a super junction structure provided by the present invention has, in the surface region of a first conductivity type drift region under a gate electrode, an undergate heavily doped N type region having a depth shallower than that of a second conductivity type body region and having a concentration higher than that of the first conductivity type drift region.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A vertical power MOSFET, comprising:
 (a) a semiconductor substrate having a first main surface and a second main surface;   (b) a cell region extending from the first main surface of the semiconductor substrate to the inside thereof;   (c) a drain region having a first conductivity type provided in the surface of the second main surface;   (d) a drift region which is provided in the cell region and in a main portion extending from a boundary with the drain region to the first main surface, and in which columnar first conductivity type drift regions and columnar second conductivity type drift regions having a conductivity type opposite to the first conductivity type are placed alternately;   (e) a gate electrode provided, via a gate insulating film, in a surface region on the side of the first main surface and over the surface of each of the columnar first conductivity type drift regions;   (f) a body region having the second conductivity type provided in the surface of the drift region on the side of the first main surface and extending from each of the columnar second conductivity type drift regions to the columnar first conductivity type drift region adjacent thereto;   (g) an undergate heavily doped N type region having the first conductivity type provided in the surface of each of the columnar first conductivity type drift regions along the gate electrode and between a pair of the body regions adjacent to each other, having a depth shallower than that of the body region, and having a concentration higher than that of the columnar first conductivity type drift region;   (h) a source region having the first conductivity type provided in the surface of each of the body regions and extending from the vicinity of the end portion of the gate electrode to the outside and having a concentration higher than that of the undergate heavily doped N type region;   (i) a metal source electrode provided over the first main surface of the semiconductor substrate and electrically coupled to the body region and the source region; and   (j) a metal drain electrode provided over the second main surface of the semiconductor substrate and electrically coupled to the drain region,   wherein the source region comprises upper surface and side surface which is extended in a direction vertical to the upper surface,   wherein the metal source electrode contacts with the side surface of the source region, and   wherein the undergate heavily doped N type region has an impurity concentration higher than that of the columnar second conductivity type drift region and lower than that of the body region.   
     
     
         2 . The vertical power MOSFET according to  claim 1 , wherein the source region is provided at a position higher than an interface between the body region and the metal source electrode. 
     
     
         3 . The vertical power MOSFET according to  claim 1 , further comprising:
 a interlayer insulating film provided so as to cover the gate electrode,   wherein the interlayer insulating film includes an upper surface and a side surface, and   wherein the side surface of the interlayer insulating film defines the side surface of the source region.   
     
     
         4 . The vertical power MOSFET according to  claim 1 , wherein the semiconductor substrate is a silicon-based semiconductor substrate. 
     
     
         5 . The vertical power MOSFET according to  claim 4 , wherein the first conductivity type is an N type. 
     
     
         6 . The vertical power MOSFET according to  claim 1 , wherein an impurity having the first conductivity type for forming the undergate heavily doped N type region is introduced by ion implantation. 
     
     
         7 . The vertical power MOSFET according to  claim 1 , wherein the impurity having the first conductivity type for forming the undergate heavily doped N type region is introduced in a region wider than a region between the pair of the body regions adjacent to each other. 
     
     
         8 . The vertical power MOSFET according to  claim 7 , wherein the impurity having the first conductivity type for forming the undergate heavily doped N type region is introduced in almost the entirety of the cell region. 
     
     
         9 . The vertical power MOSFET according to  claim 8 , wherein the gate electrode is provided over the entire surface of a portion facing onto the undergate heavily doped N type region. 
     
     
         10 . The vertical power MOSFET according to  claim 9 , which is for use in a motor drive. 
     
     
         11 . The vertical power MOSFET according to  claim 8 , which is a planar gate type. 
     
     
         12 . The vertical power MOSFET according to  claim 8 , which is a trench gate type.

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