Display device and method of fabricating the same

Abstract

A display device and method of fabricating the same are disclosed. In one aspect, the display device includes a substrate, a black matrix formed over the substrate, and a transparent electrode formed over the substrate. The black matrix and the transparent electrode have first and second areas, respectively. The sum of the first and second areas is substantially equal to the surface area of the substrate.

What is claimed is: 
     
         1 . A method of fabricating a display device, the method comprising:
 forming a gate pattern including a gate electrode, a gate line, and a gate pad over a substrate;   forming a data pattern including a semiconductor pattern, a source electrode, a drain electrode, a data line, and a data pad over the substrate; and   forming a black matrix and a transparent electrode over the substrate based on a single mask,   wherein the black matrix has a first area and the transparent electrode has a second area, and   wherein the sum of the first and second areas is substantially equal to the surface area of the substrate.   
     
     
         2 . The method of  claim 1 , wherein the one mask is a halftone mask or a slit mask. 
     
     
         3 . The method of  claim 1 , wherein the forming of the black matrix and the transparent electrode comprises:
 forming a black matrix layer over the substrate;   etching one or more portions of the black matrix layer based on the mask so as to form a black matrix pattern;   etching one or more portions of the black matrix pattern so as to form a black matrix;   forming a transparent electrode layer over the black matrix;   forming a photoresist layer over the transparent electrode layer;   forming a photoresist pattern over the black matrix by etching a portion of the photoresist layer, wherein the photoresist pattern exposes one or more portions of the transparent electrode layer;   etching the exposed portions of the transparent electrode layer based on masking by the photoresist pattern; and   removing the photoresist pattern.   
     
     
         4 . The method of  claim 3 , wherein the mask comprises a first area blocking emitted light, a second area transmitting a portion of light and blocking the remaining portion of the light, and a third area transmitting the emitted light. 
     
     
         5 . The method of  claim 4 , wherein the forming of the black matrix pattern comprises forming a black matrix pattern including a first black matrix corresponding to the first area and a second black matrix corresponding to the second area. 
     
     
         6 . The method of  claim 5 , wherein the forming of the black matrix comprises etching a portion of the first black matrix and the entire second black matrix. 
     
     
         7 . The method of  claim 3 , further comprising:
 forming a first insulating layer between the gate pad and the data pad; and   forming a second insulating layer over the data pad and the first insulating layer.   
     
     
         8 . The method of  claim 7 , wherein the forming of the black matrix pattern comprises:
 etching a portion of the first and second insulating layers so as to form a gate contact hole overlapping a portion of the gate pad by; and   etching a portion of the second insulating layer so as to form a data contact hole overlapping a portion of the drain electrode and a data contact hole overlapping a portion of the data pad.   
     
     
         9 . The method of  claim 8 , wherein the forming of the black matrix pattern comprises etching a black matrix layer overlapping the drain contact hole, the gate contact hole, and the data contact hole. 
     
     
         10 . The method of  claim 8 , wherein the forming of the black matrix pattern comprises substantially simultaneously etching a portion of the black matrix layer, the first insulating layer, and the second insulating layer. 
     
     
         11 . The method of  claim 3 , wherein the forming of the photoresist layer comprises planarizing the photoresist layer. 
     
     
         12 . The method of  claim 1 , wherein the forming of the gate pattern further comprises forming a capacitor electrode spaced apart from the gate electrode. 
     
     
         13 . The method of  claim 1 , wherein the first area comprises a projection onto the substrate and wherein the second area comprises a projection onto the substrate.