Integrated circuit with electrical fuse and method of forming the same

Abstract

A method of forming an integrated circuit. The method includes forming at least one transistor and at least one electrical fuse over a substrate. Forming the at least one transistor includes forming a gate dielectric structure over a substrate and a work-function metallic layer over the gate dielectric structure. Forming the at least one transistor further includes forming a conductive layer over the work-function metallic layer and a source/drain (S/D) region being disposed adjacent to each sidewall of the gate dielectric structure. Forming the at least one transistor further includes forming a diffusion barrier layer between the gate dielectric structure and the work-function layer. Forming the at least one electrical fuse includes forming a first semiconductor layer over the substrate. Forming the at least one electrical fuse includes forming a first silicide layer on the first semiconductor layer, wherein the diffusion barrier layer is formed before the first silicide layer.

What is claimed is: 
     
         1 . A method of forming an integrated circuit, the method comprising:
 forming at least one transistor over a substrate, wherein forming the at least one transistor comprises:   forming a gate dielectric structure over a substrate;   forming a work-function metallic layer over the gate dielectric structure;   forming a conductive layer over the work-function metallic layer; and   forming a source/drain (S/D) region being disposed adjacent to each sidewall of the gate dielectric structure;   forming a diffusion barrier layer between the gate dielectric structure and the work-function layer; and   
       forming at least one electrical fuse over the substrate, wherein forming the at least one electrical fuse comprises:
 forming a first semiconductor layer over the substrate; and 
 forming a first silicide layer on the first semiconductor layer, wherein the diffusion barrier layer is formed before the first silicide layer. 
 
     
     
         2 . The method of  claim 1 , wherein the work-function metallic layer is formed after forming the first silicide layer. 
     
     
         3 . The method of  claim 2 , wherein forming the work-function metallic layer and forming the conductive layer comprise:
 forming a second semiconductor layer over the diffusion barrier before forming the silicide layer;   forming a second silicide layer on the second semiconductor layer;   forming a cap layer covering the first silicide layer and exposing the second silicide layer;   removing the second silicide layer and the second semiconductor layer to form a first opening that is left by the removed second silicide layer and the second semiconductor layer; and   sequentially forming the work-function metallic layer and the conductive layer in the first opening.   
     
     
         4 . The method of  claim 3 , wherein forming the first semiconductor layer over the substrate and forming the second semiconductor layer over the diffusion barrier layer comprise:
 forming a diffusion barrier material over the substrate;   removing a portion of the diffusion barrier material to form a second opening in the remaining diffusion barrier material;   forming a semiconductor material on the remaining diffusion barrier material; and   removing portions of the semiconductor material and the remaining diffusion barrier material, such that first semiconductor layer is formed over the substrate and the second semiconductor layer is formed over the diffusion barrier layer.   
     
     
         5 . The method of  claim 1 , wherein the diffusion barrier layer and the work-function metallic layer are formed before forming the first silicide layer. 
     
     
         6 . The method of  claim 1 , further comprising:
 forming a second semiconductor material on the conductive layer.   
     
     
         7 . The method of  claim 5 , wherein forming the first semiconductor layer over the substrate and forming the second semiconductor material on the conductive layer comprise:
 forming a gate dielectric structure over the substrate;   forming a diffusion barrier material over the gate dielectric structure;   forming a work-function metallic material over the diffusion barrier material;   forming a conductive material over the work-function metallic material;   removing portions of the diffusion barrier material, the work-function metallic material and the conductive material to form an opening in the remaining diffusion barrier material, the remaining work-function metallic material and the remaining conductive material;   forming a semiconductor material on the remaining conductive material and filling in the opening; and   removing portions of the semiconductor material, the remaining diffusion barrier material, the remaining work-function metallic material and the remaining conductive material, such that first semiconductor layer is formed over the substrate and the second semiconductor layer is formed on the conductive layer.   
     
     
         8 . A method of forming an integrated circuit, the method comprising:
 forming a first semiconductor layer in a transistor region over a substrate and a second semiconductor layer in a fuse region over the substrate;   forming a first silicide layer on the first semiconductor layer and a second silicide layer on the second semiconductor layer;   forming a dielectric layer around the first and second semiconductor layers, exposing the first and second silicide layers;   forming a cap layer covering the second silicide layer and exposing the first silicide layer;   removing the first silicide layer and the first semiconductor layer to form a first opening that is left by the removed first silicide layer and the removed first semiconductor layer;   sequentially forming a work-function metallic layer and a conductive layer in the first opening; and   forming a diffusion barrier between the substrate and the work-function metallic layer, wherein the diffusion barrier is formed before the first silicide layer.   
     
     
         9 . The method of  claim 8 , wherein the work-function metallic layer is formed after forming the first silicide layer. 
     
     
         10 . The method of  claim 9 , wherein forming the first semiconductor layer over the substrate and forming the second semiconductor layer over the diffusion barrier comprise:
 forming a diffusion barrier material over the substrate;   removing a portion of the diffusion barrier material to form a second opening in the remaining diffusion barrier material;   forming a semiconductor material on the remaining diffusion barrier material; and   removing portions of the semiconductor material and the remaining diffusion barrier material, such that first semiconductor layer is formed over the substrate and the second semiconductor layer is formed over the diffusion barrier.   
     
     
         11 . An integrated circuit comprising:
 at least one transistor and at least one electrical fuse disposed over the substrate, wherein the at least one transistor comprises:
 a gate dielectric structure over the substrate; 
 a work-function layer over the gate dielectric structure; 
 a conductive layer over the work-function metallic layer; and 
 a source/drain (S/D) region adjacent to each sidewall of the gate dielectric structure; 
 a diffusion barrier between the gate dielectric structure and the work-function layer; and 
 wherein the at least one electrical fuse comprises: 
 a first semiconductor layer over the substrate; and 
   a first silicide layer on the first semiconductor layer.   
     
     
         12 . The integrated circuit of  claim 11 , wherein the diffusion barrier continuously extend around the work-function layer. 
     
     
         13 . The integrated circuit of  claim 11 , further comprising a second semiconductor layer over the conductive layer. 
     
     
         14 . The integrated circuit of  claim 13 , further comprising a second silicide layer over the second semiconductor layer, wherein a top surface of the second silicide layer is substantially leveled with a top surface of the first silicide layer. 
     
     
         15 . The integrated circuit of  claim 11 , wherein the at least one electrical fuse further comprises a dielectric layer between the first semiconductor layer and the substrate. 
     
     
         16 . The integrated circuit of  claim 11 , further comprising an isolation feature in the substrate, wherein the first semiconductor layer is over the isolation feature. 
     
     
         17 . The integrated circuit of  claim 11 , wherein the S/D region extends above a top surface of the substrate. 
     
     
         18 . The integrated circuit of  claim 11 , wherein the work function layer contacts sidewalls of the conductive layer. 
     
     
         19 . The integrated circuit of  claim 11 , wherein the at least one transistor further comprises spacers, and the work function layer directly contacts the spacers. 
     
     
         20 . The integrated circuit of  claim 11 , wherein the at least one transistor further comprises spacers, and the diffusion barrier is between the work function layer and the spacers.