Liquid crystal display

Abstract

In one embodiment of the present invention, each pixel includes first and second subpixels. CS bus lines connected to the respective storage capacitors of the first and second subpixels are electrically independent of each other. A CS voltage has a waveform that inverts its polarity at least once a frame, which includes a first subframe for sequentially scanning a series of odd rows and a second SF for sequentially scanning even rows that have been skipped during the first SF. A source signal voltage varies so as to have two frames or subframes with mutually opposite polarities. A CS voltage has a waveform that has quite opposite consequences on the effective voltage of a subpixel of a pixel connected to the j th scan line to be selected during the first subframe and on that of another subpixel of a pixel connected to the (j+1) th scan line to be selected during the second subframe. In this manner, the deterioration in display quality, which would be caused if either a source line inversion drive or a block inversion drive is applied to a multi-pixel technology, can be minimized.

1 - 23 . (canceled) 
     
     
         24 . A gate driver comprising:
 a first shift register for odd stages and a second shift register for even stages, the first and second shift registers receiving clock signals and start pulses independently of each other;   a first AND gate that receives the output of one of the first and second shift registers and a logically inverted one of the control signal; and   a second AND gate that receives the output of the other shift register and a logically inverted one of the control signal that has already had its logic inverted,   wherein the respective outputs of the first and second AND gates correspond to signals to be output to their associated gate bus lines.   
     
     
         25 . The gate driver of  claim 24 , wherein it is determined by the control signal whether output needs to be provided from an odd stage through the first shift register or an even stage through the second shift register.