Receiver with Clock Recovery Circuit and Adaptive Sample and Equalizer Timing

Abstract

A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.

What is claimed is: 
     
         1 . A receiver comprising:
 a data input port;   an edge sampler coupled to the data input port;   clock recovery circuitry having a clock-recovery input port, coupled to the data input port via the edge sampler, and a clock-recovery output port;   a data sampler having a data-sampler input terminal, coupled to the data input port, and a data-sampler output terminal;   an equalizer coupled to the data-sampler input terminal, the equalizer having an equalizer clock terminal; and   an adaptive phase-offset controller coupled between the clock-recovery output port of the clock recovery circuitry and the equalizer clock terminal, the phase-offset controller having a phase-offset control port.