Non-volatile memory having individually optimized silicide contacts and process therefor

Abstract

In an integrated-circuit memory, performance is increased by reducing an electrical contact resistance between a metal layer and an upper poly layer (a control gate poly). The electrical contact resistance is reduced by increasing the thickness of a silicide layer between the metal layer and the upper poly layer. The memory has a memory cell region and a non-memory cell region. The thickness of the silicide layer is typically restricted by consideration of integrated-circuit fabrication geometry for each memory cell not to exceed a predetermined aspect ratio. The present implementation allows independent optimization of the thickness of silicide layer in the memory cells region and the non-memory cell region. In particular, in the non-memory cell region, a thicker silicide layer significantly improves the contact resistance of a slit contact for components having the upper poly layer in contact with a lower poly layer (a floating gate poly).

It is claimed: 
     
         1 . A memory integrated circuit, comprising:
 channels regions formed on a substrate;   a floating gate polysilicon layer above and isolated from the channel regions;   a first polysilicon layer above and isolated from the floating gate polysilicon layer;   a first metal silicide layer above and in electric contact with the first polysilicon layer; and   a metal layer above and in electric contact with the metal silicide layer; and wherein:   in a first region of said memory integrated circuit where nonvolatile memory elements are formed, said first metal silicide layer has a first thickness; and   in a second region of said memory integrated circuit where other circuit elements are formed with contacts below said first metal layer, a second metal silicide layer is formed below the first metal layer, said second metal silicide layer has a second thickness that exceeds the first thickness by a predetermined amount.   
     
     
         2 . The memory integrated circuit as in  claim 1 , wherein in said first region:
 individual portions of said first polysilicon layer serves as control gates for the nonvolatile memory elements.   
     
     
         3 . The memory integrated circuit as in  claim 1 , wherein in said second region:
 individual portions of said first polysilicon layer serve as control gates for select transistors for the nonvolatile memory elements in said first region;   each select transistor having an individual polysilicon plug electrically connecting between a corresponding individual portion of said first polysilicon layer and a corresponding portion of said floating gate polysilicon layer.   
     
     
         4 . The memory integrated circuit as in  claim 1 , wherein:
 said second region includes non-memory components with slit contacts to the metal layer;   each slit contact enables the metal layer to dip down to make contact with the floating gate polysilicon layer;   said second metal silicide layer is between the metal layer and the floating gate polysilicon layer.   
     
     
         5 . The memory integrated circuit as in  claim 1 , wherein the first polysilicon layer and the metal layer have a uniform thickness across the first and second regions. 
     
     
         6 . The memory integrated circuit as in  claim 1 , wherein the nonvolatile memory elements are organized as NAND type memory. 
     
     
         7 . The memory integrated circuit as in  claim 1 , wherein the nonvolatile memory elements are organized in a two-dimensional array. 
     
     
         8 . The memory integrated circuit as in  claim 1 , wherein the nonvolatile memory elements are part of a three-dimensional array. 
     
     
         9 . The memory integrated circuit as in  claim 1 , wherein each of the nonvolatile memory elements each stores more than one bit of data. 
     
     
         10 . A method of forming a memory, comprising:
 forming a multi-layer slab on top of a semiconductor substrate with layers corresponding to structures of an array of NAND strings, and wherein the layers includes a first region for forming memory cells of the NAND strings and a second region for forming select transistors and peripheral circuits components, and wherein a first polysilicon layer is deposited as a top layer of the multi-layer slab;   masking the first polysilicon layer with a mask layer that leaves unmasked areas in designated areas among the second region;   etching trenches in the unmasked areas;   depositing a second polysilicon layer in the trenches;   etching back the second polysilicon layer to the mask layer;   depositing a first metal layer;   annealing to form a first silicide layer between the first metal layer and the second polysilicon layers interfacing with the first metal layer;   removing the first metal layer;   removing the mask layer to expose the first polysilicon layer;   depositing a second metal layer; and   annealing to form a second silicide layer between the second metal layer and the first polysilicon layer.   
     
     
         11 . The method as in  claim 10 , wherein:
 the peripheral circuits components include slit contacts;   said etching back the second polysilicon layer to the mask layer also creates at each slit contact an exposed portion of a floating gate polysilicon below the first polysilicon layer; and   said annealing to form a first silicide layer between the first metal layer and the second polysilicon layers interfacing with the first metal layer also has the first silicide layer formed between the first metal layer and the exposed floating gate polysilicon.   
     
     
         12 . The method as in  claim 10 , wherein:
 the first and second metal layers are tungsten.   
     
     
         13 . The method as in  claim 10 , wherein:
 the first polysilicon layer is for forming a portion of the control gates of the memory cells.   
     
     
         14 . The method as in  claim 10 , wherein:
 the first polysilicon layer is doped.   
     
     
         15 . The method as in  claim 10 , wherein:
 the second polysilicon layer is for forming poly plugs that connect between the first polysilicon layer and a floating-gate polysilicon layer.   
     
     
         16 . A method of forming a memory having memory cells arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions, said method comprising:
 forming a multi-layer slab on top of a semiconductor substrate in an x-y plane, the layers of the multi-layer slab being stacked in the z-direction and corresponding to structures of an array in the x-y plane of NAND memory cells, and wherein the layers includes a first region for forming memory cells of the NAND strings and a second region for forming select transistors and peripheral circuits components, and wherein a first polysilicon layer is deposited as a top layer of the multi-layer slab;   masking the first polysilicon layer with a mask layer that leaves unmasked areas in designated areas among the second region;   etching trenches in the unmasked areas;   depositing a second polysilicon layer in the trenches;   etching back the second polysilicon layer to the mask layer;   depositing a first metal layer;   annealing to form a first silicide layer between the first metal layer and the second polysilicon layers interfacing with the first metal layer;   removing the first metal layer;   removing the mask layer to expose the first polysilicon layer;   depositing a second metal layer; and   annealing to form a second silicide layer between the second metal layer and the first polysilicon layer.   
     
     
         17 . The method as in  claim 16 , wherein:
 the peripheral circuits components include slit contacts;   said etching back the second polysilicon layer to the mask layer also creates at each slit contact an exposed portion of a floating gate polysilicon below the first polysilicon layer; and   said annealing to form a first silicide layer between the first metal layer and the second polysilicon layers interfacing with the first metal layer also has the first silicide layer formed between the first metal layer and the exposed floating gate polysilicon.   
     
     
         18 . The method as in  claim 16 , wherein:
 the first and second metal layers are tungsten.   
     
     
         19 . The method as in  claim 16 , wherein:
 the first polysilicon layer is for forming a portion of the control gates of the memory cells.   
     
     
         20 . The method as in  claim 16 , wherein:
 the second polysilicon layer is for forming poly plugs that connect between the first polysilicon layer and a floating-gate polysilicon layer.