Series resistance reduction in vertically stacked silicon nanowire transistors

Abstract

Embodiments are directed to a method of fabricating a portion of a nanowire field effect transistor (FET). The method includes forming a sacrificial layer and a nanowire layer, removing a sidewall portion of the sacrificial layer and forming a diffusion block in a space that was occupied by the removed sidewall portion of the sacrificial layer. The method further includes forming a source region and a drain region such that the diffusion block is between the sacrificial layer and at least one of the source region and the drain region, and removing the sacrificial layer using a sacrificial layer removal process, wherein the diffusion block prevents the sacrificial layer removal process from also removing portions of at least one of the source region and the drain region.

What is claimed is: 
     
         1 . A nanowire field effect transistor (FET) comprising:
 a nanowire channel layer having a first end region;   a diffusion block formed under the first end region of the nanowire channel layer; and   a source region or a drain region positioned adjacent the diffusion block and the first end region of the nanowire channel;   wherein the diffusion block comprises a material having a selectivity to predetermined fabrication operations of the FET;   wherein the selectivity of the diffusion block prevents the predetermined fabrication operations of the FET from removing portions of the source region or the drain region.   
     
     
         2 . The nanowire FET of  claim 1 , wherein the predetermined fabrication operations of the FET comprise wet processes. 
     
     
         3 . The nanowire FET of  claim 2 , wherein a selectivity of the wet process to the diffusion block is below a predetermined threshold. 
     
     
         4 . The nanowire FET of  claim 2 , wherein the wet process comprises an etch. 
     
     
         5 . The nanowire FET of  claim 4 , wherein the etch comprises a reactive ion etch. 
     
     
         6 . The nanowire FET of  claim 5 , wherein the reactive ion etch causes an etch rate of the diffusion block that is below a predetermined threshold. 
     
     
         7 . The nanowire FET of  claim 1  further comprising a plurality of nanowire channel layers. 
     
     
         8 . The nanowire FET of  claim 1  further comprising:
 a gate region around the nanowire channel layer; 
 wherein the gate region controls a flow of current through the nanowire channel layer. 
 
     
     
         9 . The nanowire FET of  claim 1 , wherein the source region or the drain region include dopants that form at least one junction. 
     
     
         10 . The nanowire FET of  claim 9 , wherein the first end region of the nanowire channel layer comprises an extension junction of the nanowire layer. 
     
     
         11 . A nanowire field effect transistor (FET) comprising:
 a nanowire channel layer having a first end region and a second end region;   a first diffusion block formed under the first end region of the nanowire channel layer;   a second diffusion block formed under the second end region of the nanowire channel layer and   a source region or a drain region positioned adjacent the first diffusion block, the second diffusion block, the first end region of the nanowire channel, and the second end region of the nanowire channel layer;   wherein the first and second diffusion blocks comprise a material having a selectivity to predetermined fabrication operations of the FET;   wherein the selectivity of the first and second diffusion blocks prevents the predetermined fabrication operations of the FET from removing portions of the source region or the drain region.   
     
     
         12 . The nanowire FET of  claim 11 , wherein the predetermined fabrication operations of the FET comprise wet processes. 
     
     
         13 . The nanowire FET of  claim 12 , wherein a selectivity of the wet processes to the first and second diffusion blocks is below a predetermined threshold. 
     
     
         14 . The nanowire FET of  claim 12 , wherein the wet processes comprise an etch. 
     
     
         15 . The nanowire FET of  claim 14 , wherein the etch comprises a reactive ion etch. 
     
     
         16 . The nanowire FET of  claim 15 , wherein the reactive ion etch causes an etch rate of the first and second diffusion blocks that is below a predetermined threshold. 
     
     
         17 . The nanowire FET of  claim 11  further comprising a plurality of nanowire channel layers. 
     
     
         18 . The nanowire FET of  claim 11  further comprising:
 a gate region around the nanowire channel layer; 
 wherein the gate region controls a flow of current through the nanowire channel layer. 
 
     
     
         19 . The nanowire FET of  claim 11 , wherein the source region or the drain region include dopants that form at least one junction. 
     
     
         20 . The nanowire FET of  claim 19 , wherein:
 the first end region of the nanowire channel layer comprises a first extension junction of the nanowire channel layer; and   the second end region of the nanowire channel layer comprises a second extension junction of the nanowire channel layer.