Semiconductor Device With Self-Aligned Back Side Features

Abstract

Various methods and devices that involve self-aligned features on a semiconductor on insulator process are provided. An exemplary method comprises forming a gate on a semiconductor on insulator wafer. The semiconductor on insulator wafer comprises a device region, a buried insulator, and a substrate. The exemplary method further comprises applying a treatment to the semiconductor on insulator wafer using the gate as a mask. The treatment creates a treated insulator region in the buried insulator. The exemplary method also comprises removing at least a portion of the substrate. The exemplary method also comprises, selectively removing the treated insulator region from the buried insulator to form a remaining insulator region after removing that portion of the substrate.

1 - 21 . (canceled) 
     
     
         22 . A semiconductor device comprising:
 a gate formed on a semiconductor on insulator wafer, wherein the semiconductor on insulator wafer comprises a device region and a buried insulator, wherein the gate is formed on a top side of the device region, and wherein the device region is less than 100 nanometers thick; and   a deposited layer located: (i) in an excavated region of the buried insulator; (ii) on a back side of the device region; and (iii) along a vertical edge of a remaining region of the buried insulator;   wherein a vertical edge of the gate is aligned to the vertical edge of the remaining region of the buried insulator within a margin of error; and   wherein the margin of error is less than 80 nanometers.   
     
     
         23 . The semiconductor device of  claim 22 , wherein:
 the deposited layer comprises a strain layer; and   the gate contacts the device region.   
     
     
         24 . The semiconductor device of  claim 22 , wherein: the deposited layer comprises a thermally conductive layer; and
 the gate is formed in the device region.   
     
     
         25 . The semiconductor device of  claim 22 , wherein:
 the semiconductor on insulator wafer comprises a second device region and a second buried insulator;   the deposited layer comprises a strain layer;   the gate contacts the second device region and is associated with a channel;   and the device region comprises a second gate associated with the channel.   
     
     
         26 . The semiconductor device of  claim 22 , wherein:
 the semiconductor device comprises an ultra-thin body region; and   the semiconductor device comprises a fully depleted silicon on insulator transistor.   
     
     
         27 . A semiconductor device comprising:
 a gate formed on a semiconductor on insulator wafer, wherein the semiconductor on insulator wafer comprises a first device region and a first buried insulator layer, wherein the gate is formed on a top side of the first device region;   a remaining portion of the first buried insulator layer formed on a back side of the gate and aligned with the gate; and   a deposited layer located: in an excavated region of the first buried insulator layer, on a back side of the first device region, and along a vertical edge of the remaining portion of the first buried insulator layer;   wherein a vertical edge of the gate is aligned to the vertical edge of the remaining portion of the first buried insulator layer.   
     
     
         28 . The semiconductor device of  claim 27 , further comprising:
 a second buried insulator layer and a second device region formed under the gate.   
     
     
         29 . The semiconductor device of  claim 28 , wherein the gate includes a gate electrode for a channel formed in the second device region; and
 wherein the first device region comprises an additional gate electrode for a channel formed in the second device region.   
     
     
         30 . The semiconductor device of  claim 28 , wherein the second buried insulator layer is thinner than the first buried insulator layer. 
     
     
         31 . The semiconductor device of  claim 27 , wherein the deposited layer comprises a strain layer. 
     
     
         32 . The semiconductor device of  claim 27 , wherein the deposited layer comprises a thermal dissipation layer. 
     
     
         33 . The semiconductor device of  claim 27 , wherein the gate is included in a transistor, the semiconductor device further comprising:
 a conductive contact extending through a patterned portion of the deposited layer coupling with the transistor.