Semiconductor device

Abstract

A semiconductor device includes a first semiconductor region of a first conductivity type, a plurality of second semiconductor regions of a second conductivity type, each comprising a first part, on the first semiconductor region, wherein the second semiconductor regions are spaced apart in a first direction, a third semiconductor region of the first conductivity type on each of the second semiconductor regions, an insulation portion between two of the second semiconductor regions, the insulation portion having one side in contact with one of the first parts and the other side in contact with one of the third semiconductor regions, a first electrode within the insulation portion, a gate electrode spaced apart from the first electrode and within the insulation portion, and a second electrode on the third semiconductor region and electrically connected to the first electrode and the third semiconductor region.

1 . A semiconductor device comprising:
 a first semiconductor region of a first conductivity type;   a plurality of second semiconductor regions of a second conductivity type, each comprising a first part, on the first semiconductor region, wherein the second semiconductor regions are spaced apart in a first direction and extend in a second direction crossing the first direction;   a third semiconductor region of the first conductivity type on each of the second semiconductor regions, the third semiconductor regions extending in the second direction parallel to the first parts;   an insulation portion between two of the second semiconductor regions, the insulation portion having one side in contact with one of the first parts and the other side in contact with one of the third semiconductor regions;   a first electrode separated from the first semiconductor region in the first direction by the insulation portion;   a gate electrode spaced apart from the first electrode, and separated from the second semiconductor region in the first direction by the insulation portion; and   a second electrode on the third semiconductor region, and electrically connected to the first electrode and the third semiconductor region.   
     
     
         2 . The device according to  claim 1 ,
 wherein surfaces of the insulation portion in contact with one of the first parts and one of the third semiconductor regions are opposite surfaces of the insulation portion in the first direction.   
     
     
         3 . The device according to  claim 1 ,
 wherein the second electrode includes a protruding portion that extends between one of the third semiconductor regions and one of the first parts.   
     
     
         4 . The device according to  claim 3 , further comprising:
 a fourth semiconductor region of the second conductivity type between the second semiconductor region and the protruding portion of the second electrode,   wherein a concentration of carriers of the second conductivity type in the fourth semiconductor region is higher than a concentration of carriers of the second conductivity type in the second semiconductor region.   
     
     
         5 . The device according to  claim 1 ,
 wherein a plurality of the third semiconductor region, the insulation portion, the first electrode, and the gate electrode is arranged in the first direction, and   wherein each of the third semiconductor regions is provided on a different one of the second semiconductor regions and in contact with one of the insulation portions that surrounds one of the gate electrodes and one of the first electrodes.   
     
     
         6 . The device according to  claim 5 ,
 wherein the first parts of the second semiconductor regions and the third semiconductor regions are alternately arranged in the first direction and not in contact with each other.   
     
     
         7 . The device according to  claim 6 ,
 wherein the spacing between the multiple gate electrodes is 2.0 μm or less, and a concentration of carriers of the first conductivity type in the first semiconductor region is 1.0×10 16  atm/cm 3  or more.   
     
     
         8 . The device according to  claim 1 ,
 wherein the spacing between the gate electrodes is 0.8 μm or more and a concentration of carriers of the first conductivity type in the first semiconductor region is 8.0×10 16  atm/cm 3  or less.   
     
     
         9 . The device according to  claim 1 ,
 wherein a concentration of carriers of the second conductivity type in a portion of the first part of the second semiconductor region is equal to or higher than a concentration of carriers of the second conductivity type in other parts of the second semiconductor region.   
     
     
         10 . A semiconductor device comprising;
 a first semiconductor region of a first conductivity type;   a second semiconductor region of a second conductivity type on the first semiconductor region;   first and second electrodes, each extending within the second semiconductor region in a first direction, the first and second electrodes being spaced from each another in a second direction crossing the first direction;   a first insulation layer separating the first electrode from the second semiconductor region and a second insulation layer separating the second electrode from the second semiconductor region; and   a third semiconductor region of the first conductivity type between the first and second insulation layers and in contact with the first insulation layer and not with the second insulation layer.   
     
     
         11 . The device of  claim 10 , further comprising a portion of the second semiconductor region between the first and second insulation layers and in contact with the second insulation layer and not with the first insulation layer, the portion of the second semiconductor region having a higher concentration of carriers of the second conductivity type than other portions of the second semiconductor region between the first and second insulation layers. 
     
     
         12 . The device of  claim 11 , further comprising a source electrode in contact with the second semiconductor region and the third semiconductor region. 
     
     
         13 . The device according to  claim 12 ,
 wherein the source electrode includes a protruding portion that extends between third semiconductor region and the portion of the second semiconductor region.   
     
     
         14 . The device according to  claim 13 , further comprising:
 a fourth semiconductor region of the second conductivity type between the second semiconductor region and the protruding portion of the source electrode,   wherein a concentration of carriers of the second conductivity type in the fourth semiconductor region is higher than a concentration of carriers of the second conductivity type in the second semiconductor region.   
     
     
         15 . The device of  claim 10 , further comprising:
 a first field plate electrode within the first insulation layer and separated from the first electrode in the first direction by the first insulation layer, the first field plate electrode being separated from the first semiconductor region in the second direction by the first insulation layer; and   a second field plate electrode within the second insulation layer and separated from the second electrode in the first direction by the second insulation layer, the second field plate electrode being separated from the first semiconductor region in the second direction by the second insulation layer.   
     
     
         16 . The device of  claim 10 , wherein the first and second electrodes are gate electrodes and the spacing between the first and second electrodes is 0.8 μm or more. 
     
     
         17 . The device of  claim 10 , wherein the first and second electrodes are gate electrodes and the spacing between the first and second electrodes is 2.0 μm or less. 
     
     
         18 . A method of manufacturing a semiconductor device, comprising:
 providing a first semiconductor region of a first conductivity type;   forming first and second gate electrodes respectively within first and second insulation regions to be spaced apart in a first direction on either side of a second semiconductor region of a second conductivity type that is on the first semiconductor region; and   forming a third semiconductor region of the first conductivity type on the second semiconductor region between the first and second insulation regions, the third semiconductor region being in contact with the first insulation region and not with the second insulation region.   
     
     
         19 . The method of  claim 18 , further comprising:
 ion-implanting carriers of the second conductivity type into a portion of the second semiconductor region, the portion having a concentration of carriers of the second conductivity type higher than other portions second semiconductor region between the first and second insulation regions and being in contact with the second insulation region and not with the first insulation region.   
     
     
         20 . The method according to  claim 19 , further comprising:
 forming a source electrode to be in contact with the second and third semiconductor regions and the portion of the second semiconductor region.