Double Side Heat Dissipation for Silicon Chip Package

Abstract

System, method, and silicon chip package for providing structural strength, heat dissipation and electrical connectivity using “W” shaped frame bonded to the one or more dies, wherein the “W” shaped frame provides compression strength to the silicon chip package when the one or more dies are bonded, and electrically conductivity between for the one or more dies to leads of silicon chip package, and heat dissipation for the silicon chip package.

1 . A method for forming a dual sided chip package comprising:
 superimposing a frame to one or more dies;   bonding the frame to the one or more dies;   molding the frame to one or more dies with an upside mold die and a downside mold die; and   singulating the frame, wherein a surface mount area of the frame is larger than surface mount area of the one or more die, and the singulating exposes heatsink surfaces of the frame.   
     
     
         2 . The method of  claim 1 , wherein the frame is configured as “W” shaped frame. 
     
     
         3 . The method of  claim 1 , wherein the frame is electrically conductive. 
     
     
         4 . The method of  claim 1 , wherein the frame is further configured as contact leads for the dual sided chip package. 
     
     
         5 . The method of  claim 1 , wherein the frame is configured to dissipate heat. 
     
     
         6 . The method of  claim 1 , the one or more dies are MOSFET components. 
     
     
         7 . The method of  claim 6 , wherein the frame is configured as source, gate and drain contacts for the MOSFET components. 
     
     
         8 . The method of  claim 1 , wherein the frame is configured in corrugated shape. 
     
     
         9 . A semiconductor chip package comprising:
 one or more dies; and   a heatsink frame bonded to the one or more dies, wherein the heatsink frame has a surface mount area larger than surface mount area of the one or more dies, and wherein the heatsink frame is a “W” shaped frame.   
     
     
         10 . The semiconductor chip package of  claim 9 , wherein the one or more dies are MOSFETs. 
     
     
         11 . (canceled) 
     
     
         12 . The semiconductor chip package of  claim 9 , wherein the semiconductor chip package is dual sided and the “W” shaped frame provides dual sided heat dissipation. 
     
     
         13 . The semiconductor chip package of  claim 9 , wherein the frame is electrically conductive. 
     
     
         14 . The semiconductor chip package of  claim 9 , wherein the frame is configured in corrugated shape. 
     
     
         15 . A system comprising:
 a processor;   a memory coupled to the processor; and   a display coupled to the processor, wherein at least one of the processor and the memory is configured as a semiconductor chip package comprising,
 one or more dies; and 
 a “W” shaped frame bonded to the one or more dies, wherein the “W” shaped frame has a surface mount area greater than surface mount area of the one or more dies and configure to provide
 dual sided heat dissipation for the chip package, and 
 electrical conductivity for the one or more dies. 
 
   
     
     
         16 . The system of  claim 15 , wherein the semiconductor chip package includes a top side and a bottom side. 
     
     
         17 . The system of  claim 15 , wherein the “W” shaped frame is electrically conductive and configured to provide connection from the one or more dies. 
     
     
         18 . The system of  claim 15 , wherein the one or more dies are MOSFETs. 
     
     
         19 . (canceled) 
     
     
         20 . The system of  claim 15 , wherein the semiconductor chip package is dual sided and the “W” shaped frame is configured to dissipate heat for the semiconductor package.