Multi-thread processor and its hardware thread scheduling method

Abstract

A multi-thread processor including a plurality of hardware threads each of which is configured to generate an independent instruction flow, a thread scheduler configured to output a thread selection signal according to a schedule, the thread selection signal being a signal for selecting a hardware thread to be used in a next execution cycle from among the plurality of hardware threads, a first selector configured to select and output an instruction generated by the hardware thread selected according to the thread selection signal, and an arithmetic circuit configured to execute the instruction output from the first selector. The thread scheduler selects at least one hardware thread selected in a fixed manner from among the plurality of hardware threads in a predetermined first execution period and selects an arbitrary hardware thread in a second execution period other than the first execution period.

What is claimed is: 
     
         1 . A multi-thread processor comprising:
 a plurality of hardware threads each of which is configured to generate an independent instruction flow;   a thread scheduler configured to output a thread selection signal according to a schedule, the thread selection signal being a signal for selecting a hardware thread to be used in a next execution cycle from among the plurality of hardware threads;   a first selector configured to select and output an instruction generated by the hardware thread selected according to the thread selection signal; and   an arithmetic circuit configured to execute the instruction output from the first selector,   wherein the thread scheduler selects at least one hardware thread selected in a fixed manner from among the plurality of hardware threads in a predetermined first execution period and selects an arbitrary hardware thread in a second execution period other than the first execution period.   
     
     
         2 . The multi-thread processor according to  claim 1 , further comprising an instruction buffer configured to store a plurality of instructions included in the instruction flow for each of the hardware threads, wherein
 the first selector selects an instruction generated by the hardware thread selected according to the thread selection signal from among the plurality of instructions stored in the instruction buffer and outputs the selected instruction.   
     
     
         3 . The multi-thread processor according to  claim 1 , further comprising:
 an instruction memory; and   an instruction fetch controller, wherein   an instruction generated by the hardware thread designated by the instruction fetch controller is fetched from the instruction memory and the fetched instruction is stored in the instruction buffer, and   the instruction fetch controller determines one of the hardware threads that generates the instruction to be fetched according to the number of instructions stored in the instruction buffer, and determines the hardware thread that generates the instruction to be stored in the instruction buffer based on the determination result.   
     
     
         4 . The multi-thread processor according to  claim 1 , wherein the thread scheduler executes the schedule in a cyclic manner. 
     
     
         5 . The multi-thread processor according to  claim 1 , wherein the thread scheduler designates the determined arbitrary hardware thread according to a predetermined algorithm in the second execution period. 
     
     
         6 . The multi-thread processor according to  claim 1 , wherein the thread scheduler comprises:
 a first scheduler configured to output a selection signal for selecting the first execution period or the second execution period and output a first hardware thread number designating the hardware thread to be used based on a predefined order of use in a period during which the selection signal designates the first execution period;   a second scheduler configured to output a second hardware thread number designating one of the plurality of hardware threads according to a predetermined algorithm; and   a second selector configured to select one of the first hardware thread number and the second hardware thread number according to the selection signal and output the selected hardware thread number as the thread selection signal.   
     
     
         7 . The multi-thread processor according to  claim 6 , wherein
 the thread scheduler comprises:
 a thread control register including a plurality of slots; 
 a counter configured to update a count value at a predetermined interval; and 
 a third selector configured to select one of the plurality of slots according to the count value and output the selection signal and the first hardware thread number based on a value stored in the selected slot, and 
   the hardware thread number and a period attribute setting flag are stored in each of the slots, the period attribute setting flag being a flag for determining a logic level of the selection signal when that slot is selected.   
     
     
         8 . The multi-thread processor according to  claim 7 , wherein the count value of the counter is reset at a predetermined interval. 
     
     
         9 . The multi-thread processor according to  claim 1 , wherein the hardware thread designated by the thread scheduler in the first execution period is set by the arithmetic circuit based on a management program, the management program being a program that is executed in the arithmetic circuit after the multi-thread processor is started up. 
     
     
         10 . A multi-thread processor comprising:
 a plurality of hardware threads each of which is configured to generate an independent instruction flow;   a thread scheduler configured to output a thread selection signal according to a schedule, the thread selection signal being a signal for selecting a hardware thread to be used in a next execution cycle from among the plurality of hardware threads;   a selector configured to select one of the plurality of hardware threads according to the thread selection signal and output an instruction generated by the selected hardware thread; and   an arithmetic circuit configured to execute the instruction output from the selector, wherein   the thread scheduler comprises:
 a scheduler configured to determine a hardware thread according to an algorithm; 
 a thread control register including a plurality of slots each of which is configured to hold first information designating one of the plurality of hardware threads or second information designating the scheduler; and 
 a storage unit configured to store third information designating one of the plurality of slots, 
   the thread scheduler successively selects slots of the thread control register starting from a first slot of the plurality of slots, and when the slot designated by the storage unit is selected, successively selects slots starting from the first slot again,   the thread scheduler makes the selector select the hardware thread designating the first information when the selected slot holds the first information, and makes the selector select the hardware thread determined by the scheduler when the selected slot holds the second information, and   the first, second and third information are set in the thread control register and the storage unit by a management program executed in the arithmetic circuit.   
     
     
         11 . The multi-thread processor according to  claim 10 , wherein
 the thread scheduler comprises a counter configured to count up a count value indicating a slot number at a predetermined interval, the counter being configured so that the count value is reset when the count value reaches a value indicated by the third information.   
     
     
         12 . The multi-thread processor according to  claim 10 , wherein
 a hardware thread number and a first period attribute setting flag are held in the slot holding the first information, the first period attribute setting flag being a flag for making the selector select the hardware thread number held in the own slot, and   a second period attribute setting flag is held in the slot holding the second information, the second period attribute setting flag being a flag for making the selector select the scheduler.   
     
     
         13 . The multi-thread processor according to  claim 10 , wherein the management program is executed after the multi-thread processor is started up. 
     
     
         14 . A multi-thread processor comprising:
 a plurality of hardware threads each of which is configured to generate an independent instruction flow;   a thread scheduler configured to output a thread selection signal, the thread selection signal being a signal for selecting a hardware thread to be used in a next execution cycle from among the plurality of hardware threads;   a selector configured to select one of the plurality of hardware threads according to the thread selection signal and output an instruction generated by the selected hardware thread; and   an arithmetic circuit configured to execute the instruction output from the selector, wherein   the thread scheduler comprises:
 a thread control register including a plurality of slots each of which is configured to hold first information and enable the first information to be rewritten; and 
 a storage unit configured to store second information designating one of the plurality of slots and enable the second information to be rewritten, 
   the thread scheduler successively selects slots of the thread control register starting from a first slot of the plurality of slots,   the thread scheduler successively selects slots starting from the first slot again when a second slot designated by the second information is selected from among the plurality of slots,   the thread scheduler makes the selector select the hardware thread based on the first information held by the successively selected slot, and   a length of a thread selection process from when the first slot is selected to when the second slot is selected can be changed by rewriting the second information.   
     
     
         15 . The multi-thread processor according to  claim 14 , wherein
 the first and second information are set in the slot and the storage unit by a management program executed in the arithmetic circuit.   
     
     
         16 . The multi-thread processor according to  claim 14 , wherein
 the thread scheduler comprises a counter configured to count up a count value indicating a slot number at a predetermined interval, the counter being configured so that the count value is reset when the count value reaches a value indicated by the third information.   
     
     
         17 . The multi-thread processor according to  claim 14 , wherein
 the first information includes a hardware thread number.   
     
     
         18 . The multi-thread processor according to  claim 14 , wherein the management program is executed after the multi-thread processor is started up. 
     
     
         19 . The multi-thread processor according to  claim 14 , further comprising:
 an instruction memory;   an instruction buffer; and   an instruction fetch controller, wherein   an instruction generated by the hardware thread designated by the instruction fetch controller is fetched from the instruction memory and the fetched instruction is stored in the instruction buffer, and   the instruction fetch controller determines the instruction generated by which of the hardware threads should be fetched according to the number of instructions stored in the instruction buffer and determines the hardware thread that generates the instruction to be stored in the instruction buffer based on the determination result.