Semiconductor apparatus with variable resistor having tapered double-layered sidewall spacers

Abstract

A method for fabricating a semiconductor apparatus includes forming a variable resistor region, and forming a spacer having a top linewidth and a bottom linewidth substantially equal to each other in the variable resistor region. The forming of the spacer includes forming a first insulating layer in the variable resistor region through a first method, forming a second insulating layer along a surface of the first insulating layer in the variable resistor region through a second method for providing step coverage superior to the first method, and etching the first and second insulating layers.

1 - 10 . (canceled) 
     
     
         11 . A semiconductor apparatus comprising:
 a lower electrode;   a variable resistor device including a first variable resistor device and a second variable resistor device, wherein the first variable resistor device is formed over and coupled to the lower electrode and has a substantially uniform width from a top to a bottom of the first variable resistor device, wherein the second variable resistor device is formed over an upper surface of and coupled to the first variable resistor device and has a width larger than that of the first variable resistor device; and   a spacer formed over an outer circumference of the first variable resistor device.   
     
     
         12 . The semiconductor apparatus of  claim 11 , further comprising:
 an upper electrode formed over and coupled to the second variable resistor device.   
     
     
         13 . The semiconductor apparatus of  claim 11 , further comprising:
 a semiconductor substrate; and   an interlayer insulating layer having a hole formed over the semiconductor substrate,   wherein the spacer and the variable resistor device are formed in the hole.   
     
     
         14 . The semiconductor apparatus of  claim 13 , wherein the spacer includes:
 a first insulating layer having a non-uniform width in the hole, and   a second insulating layer formed over a surface of the first insulating layer and having a substantially uniform width.   
     
     
         15 . The semiconductor apparatus of  claim 14 , wherein the first insulating layer has substantially the same etch selectivity as the second insulating layer.