3D Memory Having Vertical Switches with Surround Gates and Method Thereof

Abstract

A vertical switching layer of a 3D memory device serves to switch a set of vertical local bit lines to a corresponding set of global bit lines, the vertical switching layer being a 2D array of TFT channels of vertical thin-film transistors (TFTs) aligned to connect to an array of local bit lines, each TFT switching a local bit line to a corresponding global bit line. The TFTs in the array have a separation of lengths Lx and Ly along the x- and y-axis respectively such that a gate material layer forms a surround gate around each TFT in an x-y plane and has a thickness that merges to form a row select line along the x-axis while maintaining a separation of length Ls between individual row select lines. The surround gate improves the switching capacity of the TFTs.

It is claimed: 
     
         1 . A method, comprising:
 forming a vertical switch layer in a 3D memory having memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions and with a plurality of parallel planes stacked in the z-direction, said memory having a multi-layer structure on top of a substrate, the multi-layer structure including a multi-plane memory layer, said forming including:
 providing in the multi-plane memory layer a 2-D array in an x-y plane of conductive pillars as bit line pillars elongated in the z-direction through the plurality of planes, the 2-D array of bit line pillars being spaced apart in the x-direction and the y-direction by a spacing Lx and a spacing Ly respectively and a difference between Ly and Lx given by a spacing Ls; 
 forming a slab of a vertical switch layer on top of the multi-plane memory layer by forming a 2D array of isolated TFT channels in the x-y plane of the slab, each TFT channel being in-line with and having a first end connected to one end of one of the bit line pillars along the z-direction; 
 depositing a layer of gate oxide on the slab; 
 forming a select gate surrounding and wrapped around each TFT channel in a plane defined by the x-direction and the y-direction by depositing a layer of gate material on top of the layer of gate oxide, said layer of gate material having a thickness that fills a space between adjacent TFT channels in the x-direction to form a select gate line along the x-direction, thereby leaving a select gate with at least half of said thickness surrounding each TFT channel while leaving a space of Ls between adjacent TFT channels along the y-direction; 
 exposing a top end of each TFT channel by selectively etching back the gate material and the oxide deposited on the top end of each TFT channel; 
 filling any pits in the vertical switch layer by depositing oxide followed by planarization; and 
 forming individual metal lines along the y-direction, each metal line in contact with a second end of a TFT channel among of a column of bit lines in the y-direction. 
   
     
     
         2 . The method as in  claim 1 , wherein said forming a 2D array of isolated TFT channels further comprises:
 depositing three layers of doped polysilicon to form a channel structure for a thin film transistor (“TFT”) aligned in the z-direction;   masking and etching portions of the three layers of doped polysilicon to form the 2D array of isolated TFT channels in the x-y plane, each TFT channel being in-line with and connected to one end of one of the bit line pillars along the z-direction.   
     
     
         3 . The method as in  claim 2 , wherein said three layers of doped polysilicon are a first layer of N+ doped polysilicon followed by a second layer of P− doped polysilicon and followed by a third layer of N+ doped polysilicon. 
     
     
         4 . The method as in  claim 1 , wherein said forming individual metal lines further comprises:
 depositing a metal layer over the vertical switch layer;   masking and etching portions of the metal layer to isolate the individual metal lines along the y-direction, each metal line in contact with the TFT channels of a column of bit lines in the y-direction; and   filling any gaps in the vertical switch layer by depositing oxide followed by planarization.   
     
     
         5 . The method as in  claim 1 , wherein:
 the conductive pillars are formed from polysilicon.   
     
     
         6 . The method as in  claim 1 , wherein:
 said filling any pits in the vertical switch layer by depositing oxide followed by planarization create an isolating oxide layer between two adjacent select gate lines; and the isolating oxide layer has a thickness given by the spacing Ls.   
     
     
         7 . The method as in  claim 6 , wherein:
 the spacing Ls gives the isolating oxide layer with a thickness that is able to withstand an operating voltage without electrical breakdown.   
     
     
         8 . The method as in  claim 1 , wherein the memory elements are non-volatile reprogrammable memory elements. 
     
     
         9 . The method as in  claim 8 , wherein the non-volatile reprogrammable memory elements each has a resistance that reversibly shift in resistance in response to a voltage applied to or current passed through the material. 
     
     
         10 . The method as in  claim 1 , wherein individual metal lines are located above the 2D array of TFT channels. 
     
     
         11 . The method as in  claim 1 , wherein individual metal lines are located below the 2D array of TFT channels