Bond pad structure for low temperature flip chip bonding

Abstract

Methods for preparing 3D integrated semiconductor devices and the resulting devices are disclosed. Embodiments include forming a first and a second bond pad on a first and a second semiconductor device, respectively, the first and the second bond pads each having plural metal segments, the metal segments of the first bond pad having a configuration different from a configuration of the metal segments of the second bond pad or having the same configuration as a configuration of the metal segments of the second bond pad but rotated with respect to the second bond pad; and bonding the first and second semiconductor devices together through the first and second bond pads.

What is claimed is: 
     
         1 . A device comprising:
 a first and a second semiconductor device having first and second bond pads, respectively, bonded together through the first and second bond pads, the first and second bond pads each having plural metal segments, the metal segments of the first bond pad having a configuration different from a configuration of the metal segments of the second bond pad or having a configuration rotated with respect to a configuration of the metal segments of the second bond pad,   wherein the metal segments of the first bond pad on the first semiconductor device comprise only columns of segments, the columns being staggered with respect to each other, and the metal segments of the second bond pad on the second semiconductor device comprise only rows of segments, the rows being staggered with respect to each other, wherein the columns of segments are perpendicular to the rows of segments.   
     
     
         2 . The device according to  claim 1 , wherein the first bond pad on the first semiconductor device is larger than the second bond pad on the second semiconductor device. 
     
     
         3 . The device according to  claim 1 , wherein the first and second bond pads each have plural copper segments. 
     
     
         4 . The device according to  claim 1 , wherein the first configuration is rotated at a 45 degree to a 90 degree angle with respect to the second configuration. 
     
     
         5 . The device according to  claim 1 , wherein the first and second semiconductor devices are bonded together through dielectric layers surrounding the first and second bond pads by a chemical or plasma activated fusion bonding process. 
     
     
         6 . The device according to  claim 1 , wherein the first and second semiconductor devices include a low temperature inorganic layer around the metal segments, and wherein the first and second bond pads and the low temperature inorganic layer are planarized on the first and second semiconductor devices, respectively, by Chemical Machine Polishing (CMP) before bonding together. 
     
     
         7 . The device according to  claim 1 , wherein the bond pads are patterned and the first and second semiconductor devices are bonded together through copper-to-copper bonds in the patterned bond pads. 
     
     
         8 . A device comprising:
 a first and a second semiconductor device having first and second bond pads, respectively, bonded together through the first and second bond pads, the first and second bond pads each having plural metal segments, the metal segments of the first bond pad having a configuration different from a configuration of the metal segments of the second bond pad or having a configuration rotated with respect to a configuration of the metal segments of the second bond pad,   wherein the metal segments of the first bond pad on the first semiconductor device comprise only columns and rows of metal islands, and the metal segments of the second bond pad on the second semiconductor device comprise only lines of segments, the lines being staggered with respect to each other, wherein the lines of segments are at a 45 degree angle to the columns and rows of metal islands.   
     
     
         9 . The device according to  claim 8 , wherein the first bond pad on the first semiconductor device is larger than the second bond pad on the second semiconductor device. 
     
     
         10 . The device according to  claim 8 , wherein the first and second bond pads each have plural copper segments. 
     
     
         11 . The device according to  claim 8 , wherein the first configuration is rotated at a 45 degree to a 90 degree angle with respect to the second configuration. 
     
     
         12 . The device according to  claim 8 , wherein the first and second semiconductor devices are bonded together through dielectric layers surrounding the first and second bond pads by a chemical or plasma activated fusion bonding process. 
     
     
         13 . The device according to  claim 8 , wherein the first and second semiconductor devices include a low temperature inorganic layer around the metal segments, and wherein the first and second bond pads and the low temperature inorganic layer are planarized on the first and second semiconductor devices, respectively, by Chemical Machine Polishing (CMP) before bonding together. 
     
     
         14 . A device comprising:
 a first and a second semiconductor device having first and second bond pads, respectively, bonded together through the first and second bond pads, the first and second bond pads each having plural metal segments, the metal segments of the first bond pad having a configuration different from a configuration of the metal segments of the second bond pad or having a configuration rotated with respect to a configuration of the metal segments of the second bond pad,   wherein the metal segments of first bond pad on the first semiconductor device comprise a first grid of rows and columns, and the metal segments of the second bond pad on the second semiconductor device comprise a second grid of rows and columns, wherein the second grid of rows and columns is at a 45 degree angle with respect to the first grid of rows and columns.   
     
     
         15 . The device according to  claim 14 , wherein the first bond pad on the first semiconductor device is larger than the second bond pad on the second semiconductor device. 
     
     
         16 . The device according to  claim 14 , wherein the first and second bond pads each have plural copper segments. 
     
     
         17 . The device according to  claim 14 , wherein the first configuration is rotated at a 45 degree to a 90 degree angle with respect to the second configuration. 
     
     
         18 . The device according to  claim 14 , wherein the first and second semiconductor devices are bonded together through dielectric layers surrounding the first and second bond pads by a chemical or plasma activated fusion bonding process. 
     
     
         19 . The device according to  claim 14 , wherein the first and second semiconductor devices include a low temperature inorganic layer around the metal segments, and wherein the first and second bond pads and the low temperature inorganic layer are planarized on the first and second semiconductor devices, respectively, by Chemical Machine Polishing (CMP) before bonding together. 
     
     
         20 . The device according to  claim 14 , wherein the bond pads are patterned and the first and second semiconductor devices are bonded together through copper-to-copper bonds in the patterned bond pads.