Fan-out package structure including antenna

Abstract

The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package including a first redistribution layer (RDL) structure having a first surface and a second surface opposite to the first substrate. The first RDL structure includes a plurality of first conductive traces close to the first surface of the first RDL structure. An antenna pattern is disposed close to the second surface of the first RDL structure. A first semiconductor die is disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure. A plurality of conductive structures is disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure. The plurality of conductive structures is spaced apart from the antenna pattern through the plurality of first conductive traces of the first RDL structure.

What is claimed is: 
     
         1 . A semiconductor package assembly, comprising:
 a first semiconductor package, comprising:
 a first redistribution layer (RDL) structure having a first surface and a second surface opposite to the first substrate, wherein the first RDL structure comprises:
 a plurality of first conductive traces close to the first surface of the first RDL structure; and 
 an antenna pattern close to the second surface of the first RDL structure; 
 
 a first semiconductor die disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure; and 
   a plurality of conductive structures disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure, wherein the plurality of conductive structures is spaced apart from the antenna pattern through the plurality of first conductive traces of the first RDL structure.   
     
     
         2 . The semiconductor package assembly as claimed in  claim 1 , wherein the first semiconductor package comprises:
 a first molding compound surrounding the first semiconductor die, being in contact with the first surface of the first RDL structure and the first semiconductor die; and   a plurality of first vias passing through the first molding compound to form a plurality of electrical connections between the first RDL structure and the plurality of conductive structures.   
     
     
         3 . The semiconductor package assembly as claimed in  claim 2 , wherein the first semiconductor die is surrounded by the plurality of vias. 
     
     
         4 . The semiconductor package assembly as claimed in  claim 2 , wherein the plurality of conductive structures is separated from the first RDL structure through the plurality of first vias and the first molding compound. 
     
     
         5 . The semiconductor package assembly as claimed in  claim 2 , wherein the first molding compound has a surface away from the first RDL structure and in a position between the plurality of first vias and the plurality of conductive structures. 
     
     
         6 . The semiconductor package assembly as claimed in  claim 1 , wherein the first semiconductor package comprises:
 a first passivation layer covering the second surface of the first RDL layer.   
     
     
         7 . The semiconductor package assembly as claimed in  claim 1 , wherein the first semiconductor package comprises:
 a second passivation layer covering the first semiconductor die, wherein the first passivation layer and the first RDL structure cover opposite surfaces of the first molding compound, respectively.   
     
     
         8 . The semiconductor package assembly as claimed in  claim 1 , wherein the first semiconductor die is spaced apart from the antenna pattern through the plurality of first conductive traces of the first RDL structure. 
     
     
         9 . The semiconductor package assembly as claimed in  claim 1 , wherein the first semiconductor die comprises a front side and a back side, and wherein pads of the first semiconductor die and the plurality of conductive structures are disposed on the front side and the back side of the first semiconductor die, respectively. 
     
     
         10 . The semiconductor package assembly as claimed in  claim 9 , wherein the first semiconductor package comprises:
 a second redistribution layer (RDL) structure disposed on the back side of the first semiconductor die, wherein the plurality of conductive structures is electrically coupled to the second RDL structure.   
     
     
         11 . The semiconductor package assembly as claimed in  claim 9 , wherein the first molding compound covers the back side of the first semiconductor die. 
     
     
         12 . The semiconductor package assembly as claimed in  claim 1 , wherein the first semiconductor die and the plurality of conductive structures are disposed close to the first surface of the first RDL structure rather than the second surface of the first RDL structure. 
     
     
         13 . The semiconductor package assembly as claimed in  claim 1 , wherein the first semiconductor package comprises:
 a second semiconductor die disposed on the first surface of the first RDL layer structure, such that the first semiconductor die and the second semiconductor die are arranged side-by-side.   
     
     
         14 . The semiconductor package assembly as claimed in  claim 9 , further comprising:
 a second semiconductor package stacked below the first semiconductor package, comprising:
 a third redistribution layer (RDL) structure disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure through the second RDL structure, wherein the third RDL structure has a third surface and a fourth surface opposite to the third surface; 
 a third semiconductor die disposed on the third surface of the third RDL structure; and 
 a second molding compound surrounding the third semiconductor die, being in contact with the third surface of the third RDL structure and the third semiconductor die. 
   
     
     
         15 . The semiconductor package assembly as claimed in  claim 14 , wherein the plurality of conductive structures is disposed on the fourth surface of the third RDL structure and electrically coupled to the first RDL structure through the third RDL structure. 
     
     
         16 . A semiconductor package assembly, comprising:
 a first semiconductor package, comprising:
 a first redistribution layer (RDL) structure having a first surface and a second surface opposite to the first substrate, wherein the first RDL structure comprises:
 an antenna pattern close to the second surface of the first RDL structure; 
 a plurality of first conductive traces close to the first surface of the first RDL structure; and 
 a first molding material filling gaps between the antenna pattern and the plurality of first conductive traces; and 
 
 a plurality of first conductive structures disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure, wherein the plurality of conductive structures is spaced apart from the antenna pattern through the plurality of first conductive traces of the first RDL structure. 
   
     
     
         17 . The semiconductor package assembly as claimed in  claim 16 , further comprising:
 a first electronic component disposed on the first surface of the first RDL structure and coupled to the first RDL structure.   
     
     
         18 . The semiconductor package assembly as claimed in  claim 17 , wherein the first electronic component is surrounded by the plurality of conductive structures. 
     
     
         19 . The semiconductor package assembly as claimed in  claim 16 , wherein a top of the antenna pattern is aligned with the second surface of the first RDL layer structure. 
     
     
         20 . The semiconductor package assembly as claimed in  claim 16 , wherein the first semiconductor package comprises:
 a first passivation layer covering the first surface of the first RDL layer, wherein the plurality of first conductive structures is formed through the first passivation layer to electrically connect to the plurality of first conductive traces.   
     
     
         21 . The semiconductor package assembly as claimed in  claim 16 , further comprising:
 a second semiconductor package stacked below the first semiconductor package, comprising:
 a second redistribution layer (RDL) structure having a third surface and a fourth surface opposite to the third surface, comprising:
 a plurality of second conductive traces, wherein the plurality of first conductive structures is disposed on the third surface of the second RDL structure and electrically coupled to the second RDL structure; and 
 a second molding material filling the gaps between the plurality of second conductive traces; and 
 
 a plurality of second conductive structures disposed on the fourth surface of the second RDL structure and electrically coupled to the second RDL structure, wherein the plurality of second conductive structures is spaced apart from the antenna pattern through the plurality of first conductive traces of the first RDL structure and the second RDL structure. 
   
     
     
         22 . The semiconductor package assembly as claimed in  claim 21 , wherein the second semiconductor package comprises a second electronic component disposed on the fourth surface of the second RDL structure. 
     
     
         23 . A semiconductor package assembly, comprising:
 a first semiconductor package, comprising:
 a first redistribution layer (RDL) structure having a first surface and a second surface opposite to the first substrate, wherein the first RDL structure comprises:
 an antenna pattern close to the second surface of the first RDL structure; and 
 
 a first semiconductor die disposed on the first surface of the first RDL structure; and 
   a plurality of conductive structures disposed on the first surface of the first RDL structure,   wherein the plurality of conductive structures is electrically coupled to the first semiconductor die through the first RDL structure, and   wherein the first semiconductor die comprises a front side and a back side, and wherein pads of the first semiconductor die and the plurality of conductive structures are disposed on the front side and the back side of the first semiconductor die, respectively.   
     
     
         24 . The semiconductor package assembly as claimed in  claim 23 , wherein the first RDL structure comprises:
 a plurality of first conductive traces close to the first surface of the first RDL structure, wherein the plurality of conductive structures is spaced apart from the antenna pattern through the plurality of first conductive traces of the first RDL structure.   
     
     
         25 . The semiconductor package assembly as claimed in  claim 23 , wherein the first semiconductor package comprises:
 a first molding compound surrounding the first semiconductor die, being in contact with the first surface of the RDL structure and the first semiconductor die; and   a plurality of first vias passing through the first molding compound to form a plurality of electrical connections between the first RDL structure and the plurality of conductive structures.   
     
     
         26 . The semiconductor package assembly as claimed in  claim 23 , wherein the first semiconductor die is surrounded by the plurality of vias. 
     
     
         27 . The semiconductor package assembly as claimed in  claim 23 , wherein the first semiconductor package comprises:
 a first passivation layer covering the second surface of the first RDL layer.   
     
     
         28 . The semiconductor package assembly as claimed in  claim 23 , wherein the first semiconductor package comprises:
 a second passivation layer covering the first semiconductor die, wherein the first passivation layer and the first RDL structure cover opposite surfaces of the first molding compound, respectively.   
     
     
         29 . The semiconductor package assembly as claimed in  claim 23 , wherein the first semiconductor package comprises:
 a second redistribution layer (RDL) structure disposed on the back side of the first semiconductor die, wherein the plurality of conductive structures is electrically coupled to the second RDL structure.   
     
     
         30 . The semiconductor package assembly as claimed in  claim 23 , wherein the first molding compound covers the back side of the first semiconductor die. 
     
     
         31 . The semiconductor package assembly as claimed in  claim 23 , wherein the first semiconductor package comprises:
 a second semiconductor die disposed on the first surface of the first RDL layer structure, such that the first semiconductor die and the second semiconductor die are arranged side-by-side.   
     
     
         32 . The semiconductor package assembly as claimed in  claim 23 , further comprising:
 a second semiconductor package stacked below the first semiconductor package, comprising:
 a third redistribution layer (RDL) structure disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure through the second RDL structure, wherein the third RDL structure has a third surface and a fourth surface opposite to the third surface; 
 a third semiconductor die disposed on the third surface of the third RDL structure; and 
 a second molding compound surrounding the third semiconductor die, being in contact with the third surface of the third RDL structure and the third semiconductor die. 
   
     
     
         33 . The semiconductor package assembly as claimed in  claim 32 , wherein the plurality of conductive structures are disposed on the fourth surface of the third RDL structure and electrically coupled to the first RDL structure through the third RDL structure.