US2017040257A1PendingUtilityA1

Hybrid subtractive etch/metal fill process for fabricating interconnects

Assignee: IBMPriority: Aug 4, 2015Filed: Aug 4, 2015Published: Feb 9, 2017
Est. expiryAug 4, 2035(~9 yrs left)· nominal 20-yr term from priority
H10W 20/0633H10P 50/264H10P 14/418H10P 14/47H10P 14/44H10P 14/43H10W 72/952H10W 72/942H10W 72/923H10W 20/039H10W 20/4432H10W 20/4421H10W 20/0698H10W 20/425H10W 20/089H10W 20/077H10W 20/067H10W 20/063H10W 20/056H10W 20/42H10W 20/038H10W 20/033H10W 20/032H10W 20/031H10W 72/90H10W 20/43H01L 21/76802H01L 21/76846H01L 21/76879H01L 23/5226H01L 23/53238
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Claims

Abstract

In one example, a method for fabricating an integrated circuit includes patterning a layer of a first conductive metal, via a subtractive etch process, to form a plurality of lines for connecting semiconductor devices on the integrated circuit. A large feature area is formed outside of the plurality of conductive lines via a metal fill process using a second conductive metal.

Claims

exact text as granted — not AI-modified
1 .- 4 . (canceled) 
     
     
         5 . A method for fabricating an integrated circuit, the method comprising:
 patterning a layer of a first conductive metal, via a subtractive etch process, to form a plurality of conductive lines for connecting semiconductor devices on the integrated circuit, wherein the patterning the layer of the first conductive metal comprises:
 depositing a first liner layer over a silicon wafer; 
 depositing the layer of the first conductive metal over the first liner layer; and 
 removing a portion of the layer of the first conductive metal down to the first liner layer; and 
 lining the plurality of lines with a second liner layer; and 
   forming a large feature area outside of the plurality of conductive lines via a metal fill process performed after the subtractive etch process, using a second conductive metal, wherein the forming the large feature area comprises:
 depositing an interlayer dielectric layer over the second liner layer; 
 patterning the interlayer dielectric layer to create a recess; 
 lining the recess with a third liner layer; and 
 depositing the second conductive metal in the recess to create the large feature area. 
   
     
     
         6 . The method of  claim 5 , wherein the metal fill process is an electroplating or vapor deposition process. 
     
     
         7 . The method of  claim 5 , wherein the large feature area is configured to house an electrical pad. 
     
     
         8 . The method of  claim 7 , wherein the large feature area overlaps with a portion of the plurality of conductive lines. 
     
     
         9 .- 20 . (canceled) 
     
     
         21 . The method of  claim 5 , wherein at least one of the first conductive metal and the second conductive metal comprises a metal alloy. 
     
     
         22 . The method of  claim 5 , wherein at least one of the first conductive metal and the second conductive metal comprises copper. 
     
     
         23 . The method of  claim 5 , wherein at least one of the first conductive metal and the second conductive metal comprises gold. 
     
     
         24 . The method of  claim 5 , wherein at least one of the first conductive metal and the second conductive metal comprises silver. 
     
     
         25 .- 31 . (canceled)

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