Liquid crystal display and method of charging/discharging pixels of a liquid crystal display

Abstract

A liquid crystal display includes a liquid crystal panel, a source driving circuit, a timing controller, and a gate driving circuit. The source driving circuit converts frame data into a plurality of data voltages, and charges/discharges a first data line according to a data voltage of the plurality of data voltages. The gate driving circuit enables a gate line corresponding to the data voltage. The timing controller sequentially enables a plurality of switch enable lines corresponding to the gate line. A plurality of pixel switches are turned on according to the enabled gate line. A data line switch is turned on according to an enabled switch enable line. The data voltage charges/discharges a corresponding pixel through the turned-on data line switch and one of the turned-on pixel switches.

What is claimed is: 
     
         1 . A liquid crystal display (LCD), comprising:
 an LCD panel comprising a plurality of pixels, wherein each pixel of the plurality of pixels is coupled to a corresponding pixel switch;   a timing controller for enabling data line switches corresponding to 2X switch enable lines;   a source driving circuit for converting image data into M data voltages for being sent to M first data lines respectively, wherein an Mi th  first data line of the M first data lines is coupled to X second data lines through X data line switches, pixels corresponding to the Mi th  first data line are charged or discharged according to an Mi th  data voltage corresponding to the Mi th  first data line, an (Mi+1) th  first data line of the M first data lines is coupled to X second data lines through X data line switches, pixels corresponding to the (Mi+1) th  first data line charged or discharged according to an (Mi+1) th  data voltage corresponding to the (Mi+1) th  first data line, an Xi th  data line switch of the X data line switches coupled to the Mi th  first data line is coupled to an corresponding second data line and an Xi th  switch enable line of the 2X switch enable lines, and an Xi′, data line switch of the X data line switches coupled to the (Mi+1) th  first data line is coupled to an corresponding second data line and an (X+Xj) th  switch enable line of the 2X switch enable lines; and   a gate driving circuit for enabling N gate lines;   wherein each pixel of an Ni th  row of pixels coupled to X second data lines corresponding to the Mi th  first data line is coupled to an (2Ni−1) th  gate line of the N gate lines through a corresponding pixel switch and located at an under side of the (2Ni−1) th  gate line and a first side of a corresponding second data line, each pixel of an Nj th , row of pixel coupled to X second lines corresponding to the (Mi+1) th  first data line is coupled to a (2Nj) th  gate line of the N gate lines through a corresponding pixel switch and located at an under side of the (2Nj) th  gate line and a second side of a corresponding second data line, a kth second data line of X second data lines coupled to the (Mi+1) th  first data line is located between a k th  second data line and a (k+i) th  second data line of X second data lines coupled to the Mi th  first data line, enable signals flowing on a gate line and a next gate line corresponding to the gate line are partially overlapping in the N gate lines, and M, N, Mi, Ni, X, Xi, Xj and k are positive integers.   
     
     
         2 . The liquid crystal display of  claim 1 , wherein duration of an enable signal flowing on each gate line of the N gate lines is equal to a sum of durations of enable signals flowing on the 2X switch enable lines. 
     
     
         3 . The liquid crystal display of  claim 1 , wherein duration of an enable signal flowing on each gate line of the N gate lines is larger than a sum of durations of enable signals flowing on the 2X switch enable lines. 
     
     
         4 . The liquid crystal display of  claim 1 , wherein a plurality of pixels corresponding to the gate line continue to be charged or discharged by a plurality of second data lines corresponding to the gate line when the enable signals flowing on the gate line and the enable signals flowing on the next gate line overlap. 
     
     
         5 . The liquid crystal display of  claim 1 , wherein each data line switch has a first terminal coupled to a corresponding first data line, a second terminal coupled to a corresponding switch enable line, and a third terminal coupled to a corresponding second data line. 
     
     
         6 . The liquid crystal display of  claim 1 , wherein each pixel switch has a first terminal coupled to a corresponding pixel, a second terminal coupled to a corresponding gate line, and a third terminal coupled to a corresponding second data line. 
     
     
         7 . A liquid crystal display (LCD), comprising:
 an LCD panel comprising a plurality of pixels arranged in rows;   a timing controller having a plurality of switch enable lines and configured to enable data line switches;   a source driving circuit configured to convert image data into data voltages and to control the plurality of pixels using the data voltages, the plurality of pixels being coupled to the source driving circuit by having each of the plurality of pixels coupled to a second data line of a plurality of second data lines, the data line switches coupling the plurality of second data lines to a first data line of a plurality of first data lines, the plurality of first data lines being coupled to the source driving circuit, a group of consecutive pixels of a row of pixels of the plurality of pixels being coupled to one first data line of the plurality of first data lines and the group of consecutive pixels of an immediately next row of pixels of the plurality of pixels being coupled to another one first data line of the plurality of first data lines; and   a gate driving circuit configured to enable the plurality of pixels, the plurality of pixels receiving enable signals from a plurality of gate lines coupled to the gate driving circuit, the group of consecutive pixels of each row of pixels being coupled to a corresponding gate line of the plurality of gate lines,   wherein a first enable signal of the enable signals for the first gate line partially overlaps a second enable signal of the enable signals for the second gate line so that a duration between a falling edge of the first enable signal for the first gate line and a raising edge of the second enable signal for the second gate line is substantially equal to a sum of durations of switch enable signals being applied to switch enable lines, of the plurality of switch enable lines, configured to enable the data line switches coupling to only the group of consecutive pixels connected to the second gate line.   
     
     
         8 . The liquid crystal display of  claim 7 , wherein duration of an enable signal being applied to each gate line of the plurality of gate lines is equal to a sum of durations enable signals being applied to the plurality of switch enable lines. 
     
     
         9 . The liquid crystal display of  claim 7 , wherein duration of an enable signal being applied to each gate line of the plurality of gate lines is larger than a sum of durations of enable signals being applied to the plurality of switch enable lines. 
     
     
         10 . The liquid crystal display of  claim 7 , wherein the row of pixels corresponding to the gate line continue to be charged or discharged by a plurality of second data lines corresponding to the gate line when the enable signals being applied to the gate line overlap the enable signals being applied to the immediately next gate line. 
     
     
         11 . The liquid crystal display of  claim 7 , wherein each data line switch has a first terminal coupled to a corresponding first data line, a second terminal coupled to a corresponding switch enable line, and a third terminal coupled to a corresponding second data line. 
     
     
         12 . The liquid crystal display of  claim 7 , wherein each pixel switch has a first terminal coupled to a corresponding pixel, a second terminal coupled to a corresponding gate line, and a third terminal coupled to a corresponding second data line.