Semiconductor device including fin having condensed channel region

Abstract

A finFET semiconductor device includes at least one semiconductor fin on an upper surface of a substrate. The semiconductor fin includes a channel region interposed between opposing source/drain regions. A gate stack is on the upper surface of the substrate and wraps around sidewalls and an upper surface of only the channel region. The channel region further includes a condensed portion formed of a first semiconductor material and a second semiconductor material. The source/drain regions are formed of the first semiconductor material while excluding the second semiconductor material.

1 .- 12 . (canceled) 
     
     
         13 . A finFET semiconductor device, comprising:
 at least one semiconductor fin on an upper surface of a substrate, the at least one semiconductor fin including a channel region interposed between opposing source/drain regions being integral with the at least one semiconductor fins so as to directly contact the source/drain regions; and   a gate stack on the upper surface of the substrate and wrapping around sidewalls and an upper surface of only the channel region;   gate spacers formed on sidewalls of the gate stack,   wherein the channel region includes a condensed portion comprising a first semiconductor material and a second semiconductor material, and the source/drain regions comprise the first semiconductor material while excluding the second semiconductor material, the condensed portion directly contacting the gate spacers.   
     
     
         14 . The finFET semiconductor device of  claim 13 , wherein the first semiconductor material is silicon (Si). 
     
     
         15 . The finFET semiconductor device of  claim 14 , wherein the second semiconductor material is germanium (Ge). 
     
     
         16 . The finFET semiconductor device of  claim 15 , wherein a concentration of Ge contained in the condensed channel portion ranges from approximately 50 to approximately 90. 
     
     
         17 . The finFET semiconductor device of  claim 15 , further comprising gate spacers formed on sidewalls of the gate stack. 
     
     
         18 . The finFET semiconductor device of  claim 13 , wherein the condensed portion does not extend beyond the gate spacers. 
     
     
         19 . The finFET semiconductor device of  claim 18 , wherein the gate spacers comprise silicon nitride (SiN). 
     
     
         20 . The finFET semiconductor device of  claim 19 , wherein the gate stack comprises a metal material. 
     
     
         21 . The finFET semiconductor device of  claim 13 , wherein a single junction is between the channel region and a first source/drain region among the opposing source/drain regions, and a single junction is between the channel region and a second source/drain region among the opposing source/drain regions.