Integrated circuit and standard cell library

Abstract

Provided is an integrated circuit including at least one cell, the at least one cell includes first and second active regions spaced apart from each other, a dummy region disposed between the first and second active regions, at least one first active fin disposed in the first active region and extending in a first direction, at least one second active fin extending along the first direction over the entire length of the second active region, and an active gate line extending in a second direction that is substantially perpendicular to the first direction, wherein the active gate line vertically overlaps the first active region and the dummy region and does not vertically overlap the second active region.

1 . An integrated circuit comprising at least one cell, the at least one cell comprises:
 first and second active regions spaced apart from each other,   a dummy region disposed between the first active region and the second active region;   at least one first active fin disposed in the first active region and extending in a first direction;   at least one second active fin extending in the first direction over the entire length of the second active region; and   an active gate line extending in a second direction that is substantially perpendicular to the first direction,   wherein the active gate line vertically overlaps the first active region and the dummy region and does not vertically overlap the second active region.   
     
     
         2 . The integrated circuit of  claim 1 , wherein the at least one cell is defined by a cell boundary having a first width in the first direction and a first height in the second direction,
 wherein the at least one second active fin vertically overlaps the cell boundary, and a first length of the at least one second active fin in the first direction is substantially the same as the first width of the cell boundary.   
     
     
         3 . The integrated circuit of  claim 1 , wherein the active gate line crosses the at least one first active fin in the first active region, and
 the first active region is a region where an NMOS transistor or a PMOS transistor is formed, and the second active region where a dummy transistor is formed.   
     
     
         4 . The integrated circuit of  claim 1 , further comprising:
 a first contact disposed on a portion of the active gate line that is vertically overlapping the dummy region; and   a plurality of second contacts disposed on the at least one first active fin and at both sides of the active gate line.   
     
     
         5 . The integrated circuit of  claim 1 , further comprising:
 a dummy gate line extending in the second direction in the second active region and spaced apart from the active gate line, and   a line cut region disposed between the dummy gate line and the active gate line.   
     
     
         6 . The integrated circuit of  claim 5 , wherein the dummy gate line and the active gate line are disposed in a straight line, with the line cut region disposed therebetween. 
     
     
         7 . The integrated circuit of  claim 5 , wherein the line cut region is disposed in the dummy region and spaced apart from each of the first active region and the second active region. 
     
     
         8 . The integrated circuit of  claim 5 , further comprising:
 a first contact disposed on a portion of the active gate line that is vertically overlapping the dummy region,   wherein the first contact and the line cut region are spaced apart from each other.   
     
     
         9 . The integrated circuit of  claim 1 , wherein a dummy gate line is not disposed in a portion of the second active region disposed in a straight line with the active gate line. 
     
     
         10 . A standard cell library comprising information about a plurality of standard cells and stored in a computer-readable storage medium,
 wherein at least one of the plurality of standard cells comprises:   a dummy region on a semiconductor substrate;   a first active region and a second active region spaced apart from each other, with the dummy region disposed therebetween;   a plurality of first active fins disposed in the first active region and extending in a first direction and disposed in parallel to one another in a second direction perpendicular to the first direction;   an active gate line extending in the second direction over the first active fins, the active gate line extending to a portion of the dummy region; and   a first contact disposed on a portion of the active gate line disposed in the dummy region, the first contact having a first width in the second direction.   
     
     
         11 . The standard cell library of  claim 10 , wherein the at least one of the plurality of standard cells further comprises:
 a plurality of second active fins extending in the first direction over the entire length of the second active region and disposed in parallel to one another in the second direction; and   a dummy gate line extending in the second direction over the second active fins, the dummy gate line extending to a portion of the dummy region.   
     
     
         12 . The standard cell library of  claim 11 , wherein the dummy gate line and the active gate line are spaced apart from each other, with a line cut region disposed therebetween. 
     
     
         13 . The standard cell library of  claim 12 , wherein the line cut region is disposed in the dummy region,
 wherein a first distance between the line cut region and the first contact in the second direction is about 0.5 times to about 5 times the first width.   
     
     
         14 . The standard cell library of  claim 11 , wherein the at least one of the plurality of standard cells further comprises:
 a plurality of second contacts disposed on the first active fins and at both sides of the active gate line; and   a plurality of third contacts disposed on the second active fins and at both sides of the dummy gate line.   
     
     
         15 . The standard cell library of  claim 10 , wherein the at least one of the plurality of standard cells further comprises:
 a plurality of second active fins extending in the first direction over an entire length of the second active region and disposed in parallel to one another in the second direction,   wherein a dummy gate line is not disposed in a portion of the second active region disposed in a straight line with the active gate line.   
     
     
         16 . A standard cell library comprising information about a plurality of standard cells and stored in a computer-readable storage medium,
 wherein at least one of the plurality of standard cells comprises:   a dummy region on a semiconductor substrate;   a first active region and a second active region spaced apart from each other, with the dummy region disposed therebetween;   a plurality of first active fins disposed in the first active region and extending in a first direction and disposed in parallel to one another along a second direction perpendicular to the first direction;   a plurality of second active fins extending in the first direction over the entire length of the second active region and disposed in parallel to one another in the second direction; and   an active gate line extending in the second direction, wherein the active gate line extends over the first active fins, vertically overlaps the first active region and the dummy region and does not vertically overlap the second active region.   
     
     
         17 . The standard cell library of  claim 16 , wherein the at least one of the plurality of standard cells further comprises:
 a dummy gate line disposed in the second active region and extending in the second direction and spaced apart from the active gate line, with a line cut region disposed therebetween.   
     
     
         18 . The standard cell library of  claim 17 , wherein the dummy gate line and the active gate line are disposed in a straight line, with the line cut region disposed therebetween. 
     
     
         19 . The standard cell library of  claim 16 , wherein the at least one of the plurality of standard cells further comprises:
 a first contact disposed on a portion of the active gate line vertically overlapping the dummy region; and   a plurality of second contacts disposed on at least one of the first active fins and at both sides of the active gate line.   
     
     
         20 . The standard cell library of  claim 16 , wherein a dummy gate line is not disposed on a portion of the second active region disposed in a straight line with the active gate line.