Semiconductor memory device and method of controlling semiconductor memory device

Abstract

A method for controlling a semiconductor storage device which includes a cell array including a plurality of memory cells; a reference circuit; a sense amplifier sensing a read current flowing through the memory cell, and a reference current flowing through the reference circuit; a write driver writing data to the memory cell; a sub cell area including the cell array, the sense amplifier, and the write driver; a memory area including a plurality of sub cell areas; and a control circuit controlling the sense amplifier and the write driver, the method including causing the control circuit to supply first write data to the sub cell area including the sense amplifier which performs a first read operation of reading data from a selected sub cell area.

What is claimed is: 
     
         1 . A method for controlling a semiconductor storage device which comprises:
 a cell array including a plurality of memory cells;   a reference circuit;   a sense amplifier sensing a read current flowing through the memory cell, and a reference current flowing through the reference circuit;   a write driver writing data to the memory cell;   a sub cell area including the cell array, the sense amplifier, and the write driver;   a memory area including a plurality of sub cell areas; and   a control circuit controlling the sense amplifier and the write driver,   the method comprising causing the control circuit to supply first write data to the sub cell area including the sense amplifier which performs a first read operation of reading data from a selected sub cell area.   
     
     
         2 . The method according to  claim 1 , wherein
 the memory cell holds data in accordance with a change in resistance value,   the sub cell area further includes:   a control logic circuit;   a first circuit discharges the read current from the cell array to a first power supply, or supplies the read current from the first power supply to the cell array, and a second circuit discharges the reference current from the reference circuit to the first power supply, or supplies the reference current to the reference circuit;   a write driver, when writing the write data to the memory cell, supplies one of an electric current and a voltage based on the write data to the memory cell, for changing the resistance value of the memory cell; and   a write data bus supplies the write data to the write driver and the control logic circuit,   the sense amplifier reads data stored in the memory cell by comparing the read current with the reference current, and   the method further comprises:   causing the control circuit to supply, to the memory area, a control signal for selecting one of   the first read operation,   a second read operation of supplying the read current to a selected memory cell without supplying the reference current, and   a third read operation of supplying the reference current to a selected reference circuit without supplying the read current;   causing the control circuit to supply first write data to the sub cell area including the sense amplifier which performs one of the first read operation, the second read operation, and the third read operation; and   causing the control logic circuit to cause the sub cell area to execute the first read operation, the second read operation, and the third read operation based on the first write data and the control signal from the control circuit.   
     
     
         3 . The method according to  claim 2 , wherein the control logic circuit operates the sense amplifier based on the first write data and the control signal. 
     
     
         4 . The method according to  claim 2 , wherein the control logic circuit operates the first circuit and the second circuit based on the first write data and the control signal.