Linearizing circuit and method for amplifier

Abstract

Linearizing circuit and method for amplifier. In some embodiments, a biasing circuit assembly for an amplifier can include a biasing circuit configured to provide a first bias signal or a second bias signal through a common node and a ballast to an input path of an amplifying transistor for operation in a first mode or a second mode, respectively. The biasing circuit assembly can further include a linearizing circuit implemented to couple the common node and a node along the input path. The linearizing circuit can be configured to improve linearity of the amplifying transistor operating in the first mode while allowing the ballast to be sufficiently robust for the amplifying transistor operating in the second mode.

What is claimed is: 
     
         1 . A biasing circuit assembly for an amplifier, comprising:
 a biasing circuit configured to provide a first bias signal or a second bias signal through a common node and a ballast to an input path of an amplifying transistor for operation in a first mode or a second mode, respectively; and   a linearizing circuit implemented to couple the common node and a node along the input path, and configured to improve linearity of the amplifying transistor operating in the first mode while allowing the ballast to be sufficiently robust for the amplifying transistor operating in the second mode.   
     
     
         2 . The biasing circuit assembly of  claim 1  wherein the ballast includes a DC ballasting resistor. 
     
     
         3 . The biasing circuit assembly of  claim 1  wherein the amplifying transistor is part of a power amplifier. 
     
     
         4 . The biasing circuit assembly of  claim 3  wherein the amplifying transistor is part of a second stage of a two-stage power amplifier. 
     
     
         5 . The biasing circuit assembly of  claim 1  wherein the amplifying transistor is a bipolar-junction transistor having a base, a collector, and an emitter, such that the input path is connected to the base. 
     
     
         6 . The biasing circuit assembly of  claim 1  wherein the linearizing circuit includes a capacitance. 
     
     
         7 . The biasing circuit assembly of  claim 6  wherein the linearizing circuit further includes a resistance connected in series with the capacitance. 
     
     
         8 . The biasing circuit assembly of  claim 6  wherein the linearizing circuit further includes an inductance connected in series with the capacitance. 
     
     
         9 . A radio-frequency module comprising:
 a packaging substrate configured to receive a plurality of components;   an amplifier implemented on a die that is mounted on the packaging substrate, the amplifier configured to amplify a radio-frequency signal; and   a biasing circuit assembly coupled to the amplifier and including a biasing circuit configured to provide a first bias signal or a second bias signal through a common node and a ballast to an input path of an amplifying transistor of the amplifier for operation in a first mode or a second mode, respectively, the biasing circuit assembly further including a linearizing circuit implemented to couple the common node and a node along the input path, and configured to improve linearity of the amplifying transistor operating in the first mode while allowing the ballast to be sufficiently robust for the amplifying transistor operating in the second mode.   
     
     
         10 . The radio-frequency module of  claim 9  wherein the amplifier is a power amplifier, and the die includes a gallium arsenide substrate configured to allow the amplifying transistor to be implemented as a heterojunction bipolar transistor. 
     
     
         11 . A wireless device comprising:
 a transceiver configured to process signals;   an amplifier in communication with the transceiver and configured to amplify a signal;   a biasing circuit assembly coupled to the amplifier and including a biasing circuit configured to provide a first bias signal or a second bias signal through a common node and a ballast to an input path of an amplifying transistor of the amplifier for operation in a first mode or a second mode, respectively, the biasing circuit assembly further including a linearizing circuit implemented to couple the common node and a node along the input path, and configured to improve linearity of the amplifying transistor operating in the first mode while allowing the ballast to be sufficiently robust for the amplifying transistor operating in the second mode; and   an antenna in communication with the amplifier and configured to facilitate operation of the wireless device with the signal.   
     
     
         12 . The wireless device of  claim 11  wherein the wireless device is a cellular phone. 
     
     
         13 . The wireless device of  claim 12  wherein the amplifier is a power amplifier and the signal includes a radio-frequency signal to be transmitted through the antenna. 
     
     
         14 . The wireless device of  claim 13  wherein the first mode includes an EDGE (enhanced data rates for GSM evolution) mode, and the second mode includes a GPRS (general packet radio service) mode. 
     
     
         15 . The wireless device of  claim 14  wherein the biasing circuit includes a current mirror that generates the first bias signal for the operation of the amplifying transistor in the EDGE mode. 
     
     
         16 . The wireless device of  claim 15  wherein the current mirror includes a bipolar junction transistor coupled to a reference current source, the first bias signal being output through an emitter of the bipolar junction transistor to be provided to the common node. 
     
     
         17 . The wireless device of  claim 16  wherein the ballast is implemented between the common node and a base of the amplifying transistor, such that the common node functions as a base-emitter junction between the base of the amplifying transistor and the emitter of the current mirror bipolar junction transistor. 
     
     
         18 . The wireless device of  claim 17  wherein the input path includes a DC blocking capacitance implemented between the base of the amplifying transistor and the node where the linearizing circuit is connected to. 
     
     
         19 . The wireless device of  claim 18  wherein the linearizing circuit is configured to couple the signal between the input path and the base-emitter junction to provide rectification on the base-emitter junction and correct AM-AM distortion and thereby provide the improved linearity. 
     
     
         20 . The wireless device of  claim 14  wherein the biasing circuit includes a bias resistance implemented between a GPRS bias node and the common node, such that the second bias signal is provided to the gate of the amplifying transistor from the GPRS bias node through the bias resistance, the common node, and the ballast.