Parallel Execution Mechanism and Operating Method Thereof

Abstract

A thread priority control mechanism is provided which uses the completion event of the preceding transaction to raise the priority of the next transaction in the order of execution when the transaction status has been changed from speculative to non-speculative. In one aspect of the present invention, a thread-level speculation mechanism is provided which has content-addressable memory, an address register and a comparator for recording transaction footprints, and a control logic circuit for supporting memory synchronization instructions. This supports hardware transaction memory in detecting transaction conflicts. This thread-level speculation mechanism includes a priority up bit for recording an attribute operand in a memory synchronization instruction, a means for generating a priority up event when a thread wake-up event has occurred and the priority up bit is 1, and a means for preventing the CAM from storing the load/store address when the instruction is a non-transaction instruction.

What is claimed is: 
     
         1 . A computer-implemented method for speculative parallel thread execution, the method comprising:
 executing a first thread in parallel with a second thread;   waiting for a notification from the first thread using a non-transaction instruction to prevent a transaction conflict; and   raising a priority of the second thread in response to receiving the notification from the first thread.   
     
     
         2 . The computer-implemented method of  claim 1 , wherein the non-transaction memory access instruction includes an inter-thread synchronization instruction and a non-transaction load instruction. 
     
     
         3 . The computer-implemented method of  claim 2 , wherein the inter-thread synchronization instruction is a memory synchronization instruction. 
     
     
         4 . The computer-implemented method of  claim 2 , wherein the non-transaction load instruction is an NTLG instruction. 
     
     
         5 . The computer-implemented method of  claim 1 , wherein raising a priority of the second thread further comprises setting a priority up bit to track an attribute of a memory synchronization instruction. 
     
     
         6 . The computer-implemented method of  claim 5 , wherein raising a priority of the second thread further comprises generating a priority up event when a thread wake-up event has occurred and the priority up bit is set. 
     
     
         7 . The computer-implemented method of  claim 6 , wherein raising a priority of the second thread further comprises preventing a content-addressable memory from storing a load/store address. 
     
     
         8 . A system for speculative parallel thread execution, the system comprising:
 a memory comprising computer readable instructions; and   a processing device for executing the computer readable instructions for performing a method, the method comprising:   executing a first thread in parallel with a second thread;   waiting for a notification from the first thread using a non-transaction instruction to prevent a transaction conflict; and   raising a priority of the second thread in response to receiving the notification from the first thread.   
     
     
         9 . The system of  claim 8 , wherein the non-transaction memory access instruction includes an inter-thread synchronization instruction and a non-transaction load instruction. 
     
     
         10 . The system of  claim 9 , wherein the inter-thread synchronization instruction is a memory synchronization instruction. 
     
     
         11 . The system of  claim 9 , wherein the non-transaction load instruction is an NTLG instruction. 
     
     
         12 . The system of  claim 8 , wherein raising a priority of the second thread further comprises setting a priority up bit to track an attribute of a memory synchronization instruction. 
     
     
         13 . The system of  claim 12 , wherein raising a priority of the second thread further comprises generating a priority up event when a thread wake-up event has occurred and the priority up bit is set. 
     
     
         14 . The system of  claim 13 , wherein raising a priority of the second thread further comprises preventing a content-addressable memory from storing a load/store address. 
     
     
         15 . A computer program product for speculative parallel thread execution, the computer program product comprising:
 a computer readable storage medium having program instructions embodied therewith, wherein the computer readable storage medium is not a transitory signal per se, the program instructions executable by a processing device to cause the processing device to perform a method comprising:   executing a first thread in parallel with a second thread;   waiting for a notification from the first thread using a non-transaction instruction to prevent a transaction conflict; and   raising a priority of the second thread in response to receiving the notification from the first thread.   
     
     
         16 . The computer program product of  claim 15 , wherein the non-transaction memory access instruction includes an inter-thread synchronization instruction and a non-transaction load instruction. 
     
     
         17 . The computer program product of  claim 16 , wherein the inter-thread synchronization instruction is a memory synchronization instruction. 
     
     
         18 . The computer program product of  claim 15 , wherein raising a priority of the second thread further comprises setting a priority up bit to track an attribute of a memory synchronization instruction. 
     
     
         19 . The computer program product of  claim 18 , wherein raising a priority of the second thread further comprises generating a priority up event when a thread wake-up event has occurred and the priority up bit is set. 
     
     
         20 . The computer program product of  claim 19 , wherein raising a priority of the second thread further comprises preventing a content-addressable memory from storing a load/store address.