Computing system and data transferring method thereof

Abstract

A computing system includes a host, at least one memory module connected with the host through a first channel, and at least one nonvolatile memory module connected with the host through a second channel. The host includes an encoder configured to encode packet data, and a memory module driver configured to transfer the encoded packet data to the at least one memory module when there is no need to decode the encoded packet data and to decode the encoded packet data using a decoder table when there is a need to decode the encoded packet data, the memory module transferring the decoded packet data to the at least one nonvolatile memory module.

What is claimed is: 
     
         1 . A computing system comprising:
 a host;   at least one memory module connected with the host through a first channel; and   at least one nonvolatile memory module connected with the host through a second channel,   wherein the host comprises:
 an encoder configured to encode packet data; and 
 a memory module driver configured to transfer encoded packet data to the at least one memory module and to decode the encoded packet data using a decoder table to transfer decoded packet data to the at least one nonvolatile memory module. 
   
     
     
         2 . The computing system of  claim 1 ,
 wherein the host and the at least one memory module transmit/receive data with each other through a double data rate (DDR) interface, and   wherein the host and the at least one nonvolatile memory module transmit/receive data with each other through the DDR interface.   
     
     
         3 . The computing system of  claim 1 , wherein the encoder performs at least one of scrambling, ECC encoding, swizzling, or randomizing with respect to the packet data. 
     
     
         4 . The computing system of  claim 1 ,
 wherein the packet data comprises slot information indicating that the at least one memory module and the at least one nonvolatile memory module are inserted, and   wherein the memory module driver determines whether to decode the encoded packet data based upon the slot information.   
     
     
         5 . The computing system of  claim 1 , wherein the decoder table is generated using initialization data transferred from the at least one nonvolatile memory module during an initialization operation of the at least one nonvolatile memory module. 
     
     
         6 . The computing system of  claim 5 , wherein the initialization data is transferred to the host from the at least one nonvolatile memory module by a mode register set (MRS) mode read operation. 
     
     
         7 . The computing system of  claim 5 , wherein a decoding function is generated using the decoder table. 
     
     
         8 . The computing system of  claim 1 ,
 wherein data is updated in a predetermined order on the at least one nonvolatile memory module, and   wherein the memory module driver generates a command table by recognizing the updated data.   
     
     
         9 . The computing system of  claim 1 ,
 wherein the at least one nonvolatile memory module comprises:
 a plurality of nonvolatile memories; 
 a buffer memory configured to temporarily store data needed for driving; and 
 a nonvolatile memory module controller configured to control the plurality of nonvolatile memories and the buffer memory, and 
   wherein the nonvolatile memory module controller comprises a RAM which exchanges data with the host through a DDR interface.   
     
     
         10 . The computing system of  claim 1 , wherein the at least one nonvolatile memory module comprises:
 a plurality of nonvolatile memories;   data buffers configured to transmit/receive data with the host;   a plurality of dynamic random access memories transmitting and receiving data of the data buffers; and   a nonvolatile memory module controller configured to control the plurality of nonvolatile memories and the plurality of dynamic random access memories and to enable the host to access the plurality of nonvolatile memories.   
     
     
         11 . The computing system of  claim 1 , wherein the at least one nonvolatile memory module comprises:
 a plurality of nonvolatile memories;   a plurality of dynamic random access memories exchanging data with the host through a DDR interface; and   a nonvolatile memory module controller configured to control the plurality of nonvolatile memories and the plurality of dynamic random access memories and to enable the host to access the plurality of nonvolatile memories.   
     
     
         12 . A data transfer method of a computing system which includes a host, at least one volatile memory module, and at least one nonvolatile memory module, the method comprising:
 scrambling packet data;   determining whether there is a need to descramble the scrambled packet data;   descrambling the scrambled packet data using a decoder table when there is a need to descramble the scrambled packet data; and   outputting the descrambled packet data to the at least one nonvolatile memory module.   
     
     
         13 . The method of  claim 12 , wherein the determining is performed based upon slot information indicating that the at least one volatile memory module or the at least one nonvolatile memory module is inserted. 
     
     
         14 . The method of  claim 12 , further comprising:
 outputting the scrambled packet data to the at least one volatile memory module when there is no need to descramble the scrambled packet data.   
     
     
         15 . The method of  claim 12 , wherein during an initialization operation of the at least one nonvolatile memory module, the decoder table is generated by transferring predetermined data between the host and the at least one nonvolatile memory module, decoding the transferred data, and comparing the transferred data and the decoded data. 
     
     
         16 . A data transfer method of a computing system which includes a host, at least one volatile memory module, and at least one nonvolatile memory module, the method comprising:
 descrambling an address, a command, data, or a serial presence detect (SPD) command;   scrambling the descrambled address, command, data or SPD command; and   transferring the scrambled address, command, data or SPD command to the at least one volatile memory module or the at least one nonvolatile memory module.   
     
     
         17 . The method of  claim 16 , wherein the scrambling comprises:
 descrambling the address and the command when defining a command between the host and the at least one volatile memory module or between the host and the at least one nonvolatile memory module.   
     
     
         18 . The method of  claim 16 , wherein the SPD command is transferred to the at least one volatile memory module or the at least one nonvolatile memory module through a side-band channel. 
     
     
         19 . The method of  claim 16 , further comprising:
 constructing the address, the command, the data, or the SPD command with a table.   
     
     
         20 . The method of  claim 16 , wherein the descrambling further comprises:
 changing a descramble manner so as to correspond to a scramble manner.