Vertical jfet made using a reduced mask set

Abstract

A vertical JFET made by a process using a limited number of masks. A first mask is used to form mesas and trenches in active cell and termination regions simultaneously. A mask-less self-aligned process is used to form silicide source and gate contacts. A second mask is used to open windows to the contacts. A third mask is used to pattern overlay metallization. An optional fourth mask is used to pattern passivation. Optionally the channel may be doped via angled implantation, and the width of the trenches and mesas in the active cell region may be varied from those in the termination region.

1 . A process for creating a vertical SiC JFET with regions of a first doping type and regions of a second doping type, comprising:
 a. starting with a SiC wafer of the second doping type, the wafer comprising a middle drift region and a bottom drain connection region;   b. adding to the wafer a top layer of the second doping type to be used as a source region;   c. using a first mask to apply a patterned hard masking layer to the top of the wafer;   d. etching trenches in a region to be used as an active device region and in a region to be used as a termination region;   e. implanting the trench bottoms with the second doping type via vertical implantation and implanting the trench sides with the second doping type via angled implantation;   f. creating oxide spacers on the trench walls via creating oxide through growth and/or deposition, followed by etching back;   g. creating gate and source contacts via depositing ohmic metal, heating to form silicides where the deposited metal is in contact with SiC, and etching away unreacted metal;   h. creating inter-layer dielectric via oxide deposition and using a second mask to create windows in the inter-layer dielectric to reach gate and source contacts;   i. creating top metallization via deposition and patterning using a third mask; and   j. creating a backside drain contact via backside processes.   
     
     
         2 . The process of  claim 1 , further comprising:
 after creating the top metallization, creating a passivation layer on top of the wafer by depositing a passivation material and using the fourth mask to open the windows top metallization.   
     
     
         3 . The process of  claim 1 , further comprising:
 after etching the trenches, implanting trench sides with the first doping type via angled implantation a first time.   
     
     
         4 . The process of  claim 3 , wherein:
 the first mask provides for narrower trenches in the termination region than in the active device region.   
     
     
         5 . The process of  claim 3 , wherein:
 the first mask provides for wider trenches in the termination region than in the active device region.   
     
     
         6 . The process of  claim 5 , further comprising:
 after implanting trench sides with the first doping type via angled implantation the first time, using a fifth mask to block implantation of the active cell region while implanting the trench sides in the termination region with the first doping type via angled implantation a second time.   
     
     
         7 . The process of  claim 6 , where:
 the second angled implanting is done at a different angle from the first angled implanting.   
     
     
         8 . The process of  claim 3 , further comprising:
 when creating oxide spacers, between the creating oxide and the etching back, using a sixth mask to prevent the etching back of the oxide in the termination region.   
     
     
         9 . The process of  claim 3 , further comprising:
 when creating gate and source contacts, prior to depositing ohmic metal, using a sixth mask to prevent to prevent deposition of the ohmic metal in the termination region.   
     
     
         10 . The process of  claim 3 , further comprising:
 after etching trenches, using a seventh mask to prevent doping of the second type from entering the trenches during the vertical implanting and the angled implanting.   
     
     
         11 . The process of  claim 3 , further comprising:
 after etching the trenches, using a seventh mask to block the termination region from implanting the trench bottoms or sidewalls with the second doping type;   then implanting the active area trench sides with the second doping type, creating oxide spacers, and creating gate and source contacts.   
     
     
         12 . The process of  claim 3 , further comprising:
 using an eighth mask to pattern the top layer of the second doping type to be used as a source region such that the top layer of the second doping type is found only in the active cell region.   
     
     
         13 . A vertical SiC JFET, comprising:
 a SiC substrate, the SiC substrate having a top, a bottom, regions of a first doping type, and regions of a second doping type, where the body of the substrate is doped with the second doping type;   a termination region comprising trenches and mesas on the top of the SiC substrate;   floating termination silicide contacts on the tops of the mesas and the bottoms of trenches in the termination region, where the floating termination silicide contacts are isolated from each other;   an active cell region comprising trenches and mesas on the top of the SiC substrate;   heavily doped source regions of the second doping type on top of the mesas in the active cell region;   source silicide contacts on top of the source regions;   gate regions of the first doping type on the sides and bottoms of the trenches in the active cell region, and;   gate silicide contacts at the bottom of the trenches in the active cell region.   
     
     
         14 . (canceled) 
     
     
         15 . (canceled) 
     
     
         16 . The vertical SiC JFET of  claim 13 , further comprising:
 regions of the first doping type on the sides and bottoms of the trenches in the termination region.   
     
     
         17 . The vertical SiC JFET of  claim 16 , further comprising:
 gaps between regions of the first doping type on the sides and bottoms of the trenches in the termination region.   
     
     
         18 . The vertical SiC JFET of  claim 16 , further comprising:
 in the trenches of the termination region, between the center of the mesas and the regions of the first doping type on the sides of the trenches, regions of doping of the second doping type that are more heavily doped than the body of the substrate.   
     
     
         19 . The vertical SiC JFET of  claim 13 , where:
 the trenches in the termination region are of a different width than the trenches in the active cell region.   
     
     
         20 . The vertical SiC JFET of  claim 13 , where:
 the mesas in the termination region are of a different width than the mesas in the active cell region.