Spacer Formation with Straight Sidewall

Abstract

Disclosed herein is a semiconductor device comprising a first dielectric disposed over a channel region of a transistor formed in a substrate and a gate disposed over the first dielectric. The semiconductor device further includes a second dielectric disposed vertically, substantially perpendicular to the substrate, at an edge of the gate, and a spacer disposed proximate to the second dielectric. The spacer includes across-section with a perimeter that includes atop curved portion and a vertical portion substantially perpendicular to the substrate. The perimeter further includes a discontinuity at an interface of the top curved portion with the vertical portion. Further, disclosed herein are methods associated with the fabrication of the aforementioned semiconductor device.

What is claimed: 
     
         1 . A semiconductor device, comprising:
 a gate comprising:
 a first dielectric disposed over a substrate; and 
 a gate layer disposed over the first dielectric; 
   a second dielectric disposed adjacent to a first gate sidewall of the gate; and   a spacer disposed adjacent to the second dielectric, wherein the spacer comprises:
 a first portion disposed over the substrate, comprising:
 a first portion sidewall which is on the opposite side of the spacer from the second dielectric and which is substantially perpendicular to the substrate; and 
 a first portion top which is substantially horizontal to the substrate; and 
 
 a second portion disposed over and in contact with the first portion top, comprising a second portion sidewall. 
   
     
     
         2 . The semiconductor device of  claim 1 , wherein:
 the first portion further comprises a first portion width measured between the second dielectric and the first portion sidewall at the first portion top;   the second portion further comprises a second portion width between the second dielectric and the second portion sidewall at the first portion top; and   the second portion width is smaller than the first portion width.   
     
     
         3 . The semiconductor device of  claim 1 , the second portion sidewall comprising an arc from the first portion top to the second dielectric. 
     
     
         4 . The semiconductor device of  claim 1 , further comprising a third dielectric disposed over the substrate adjacent to the second dielectric wherein the first portion is disposed over the third dielectric. 
     
     
         5 . The semiconductor device of  claim 4 , wherein the second dielectric and the third dielectric comprise the same material. 
     
     
         6 . The semiconductor device of  claim 1 , further comprising a first doped region in the substrate adjacent to the first portion sidewall and a second doped region in the substrate adjacent to a second gate sidewall which is on the opposite side of the gate from the first gate sidewall. 
     
     
         7 . The semiconductor device of  claim 1 , wherein the first dielectric comprises a charge dielectric. 
     
     
         8 . The semiconductor device of  claim 7 , wherein the first dielectric further comprises a nitride layer between two oxide layers. 
     
     
         9 . The semiconductor device of  claim 1 , wherein the :ate layer comprises polycrystalline silicon. 
     
     
         10 . The semiconductor device of c aim  1 , wherein the second dielectric comprises silicon dioxide. 
     
     
         11 . The semiconductor device of  claim 1 , wherein the spacer comprises polycrystalline silicon. 
     
     
         12 . The semiconductor device of  claim 1 , wherein the first gate is a memory gate and the spacer is a select gate. 
     
     
         13 . An integrated circuit device, comprising:
 a substrate;   a gate structure having a gate conducting layer and a gate dielectric layer between the gate conducting layer and the substrate;   a first inter-gate dielectric structure disposed adjacent to a first gate sidewall of the gate structure;   a second inter-gate dielectric structure disposed adjacent to a second gate sidewall of the gate structure;   a first spacer structure disposed adjacent to the first inter-gate dielectric structure, having a first spacer layer and a first spacer dielectric layer between the first spacer layer and the substrate; and   a second spacer structure disposed adjacent to the second inter-gate dielectric structure having a second spacer layer and a second spacer dielectric layer between the second spacer layer and the substrate;   wherein the first spacer layer and the second spacer layer each comprises:
 a corresponding lower spacer portion disposed over the corresponding spacer dielectric layer comprising a lower spacer portion sidewall on the opposite side of the corresponding lower spacer portion from the corresponding inter-gate dielectric structure, wherein the corresponding lower spacer portion sidewall is substantially perpendicular to the substrate, and further comprising a corresponding lower spacer portion top surface which is substantially horizontal to the substrate; and 
 a corresponding upper spacer portion disposed directly over the corresponding lower spacer portion top surface comprising a corresponding upper spacer portion sidewall which comprises an arc from the corresponding lower spacer portion top surface to the corresponding inter-gate dielectric structure. 
   
     
     
         14 . The integrated circuit device of  claim 13 , wherein:
 each of the lower spacer portions further comprises a corresponding lower spacer portion width measured between the corresponding inter-gate dielectric structure and the corresponding lower spacer portion sidewall at the corresponding lower spacer portion top surface;   each of the upper spacer portions further comprises a corresponding upper spacer portion width measured between the corresponding inter-gate dielectric structure and the corresponding upper spacer portion sidewall at the corresponding lower spacer portion top surface; and   the corresponding upper spacer portion width is smaller than the corresponding lower spacer portion width.   
     
     
         15 . The integrated device of  claim 13 , wherein the spacer dielectric layers and the inter-gate dielectric structures comprise the same material. 
     
     
         16 . The integrated device of  claim 13 , wherein the gate dielectric layer comprises a charge trapping dielectric. 
     
     
         17 . The integrated device of  claim 16 , wherein the gate dielectric layer further comprises a nitride layer between two oxide layers. 
     
     
         18 . The integrated device of  claim 13 , wherein the gate conducting layer comprises polycrystalline silicon. 
     
     
         19 . The integrated device of  claim 13 , wherein the inter-gate dielectric structure comprise silicon dioxide. 
     
     
         20 . A memory integrated circuit (IC), comprising:
 a substrate;   a memory device formed on e substrate, wherein the memory device comprises:
 a memory gate comprising a first dielectric disposed over a channel region formed in the substrate and a first gate layer disposed over the first dielectric; 
 a second dielectric disposed adjacent to a first memory gate sidewall of the memory gate; 
 a select gate adjacent to the second dielectric comprising a third dielectric disposed over the substrate and a select gate layer disposed over the third dielectric, the select gate layer comprising a select gate sidewall on the opposite side of the select gate layer from the second dielectric wherein the select gate sidewall comprises:
 a vertical portion which is substantially perpendicular to the substrate; and 
 a curved portion comprising an arc from the first portion to the second dielectric; 
 wherein the select gate sidewall comprises a discontinuity between the vertical portion and the curved portion; and 
 
 a first doped region in the substrate adjacent to the select gate and a second doped region in the substrate adjacent to the memory gate. 
   
     
     
         21 . The memory IC of  claim 20 , wherein the discontinuity is a horizontal portion substantially parallel to the substrate.